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mos integrated circuit pd17240,17241,17242,17243,17244,17245,17246 description the pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (hereafter called the pd17246 subseries) are 4- bit single-chip microcontrollers for small general-purpose infrared remote control transmitters. this subseries employs 17k general-purpose register system architecture for the cpu, and can directly execute operations between data memories instead of the conventional method of executing operations through an accumulator. moreover, all the instructions are 16-bit/1-word instructions, enabling efficient programming. in addition, a one-time prom model, the pd17p246, to which data can be written only once, is also available. this product is convenient either for evaluating the pd17246 subseries programs or for small-scale production of application systems. detailed function descriptions are provided in the following user's manual. be sure to read them before designing. pd172 subseries user's manual: u12795e features infrared remote controller carrier generator (rem output) 17k architecture: general-purpose register system program memory (rom), data memory (ram) pd17240 pd17241 pd17242 pd17243 pd17244 pd17245 pd17246 program 4 kb 8 kb 12 kb 16 kb 20 kb 24 kb 32 kb memory (rom) (2,048 16) (4,096 16) (6,144 16) (8,192 16) (10,240 16) (12,288 16) (16,384 16) data memory 447 4 bits (ram) 8-bit timer: 1 channel basic interval timer/watchdog timer: 1 channel instruction execution time (can be changed in two steps) @ f x = 4 mhz: 4 s (high-speed mode)/8 s (normal mode) external interrupt pin (int/p1b 0 ): 1 i/o pins: 24 supply voltage: v dd = 2.0 to 3.6 v on-chip ram retention detector low-voltage detector (mask option) unless otherwise specified, the pd17246 is treated as the representative model throughout this document. document no. u15002ej1v0ds00 (1st edition) date published april 2003 n cp (k) printed in japan 4-bit single-chip microcontrollers for small general-purpose infrared remote control transmitters data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. c the mark shows major revised points.
2 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 applications preset remote controllers, toys, portable systems, etc. ordering information part number package pd17240mc- -5a4 30-pin plastic ssop (7.62 mm (300)) pd17241mc- -5a4 30-pin plastic ssop (7.62 mm (300)) pd17242mc- -5a4 30-pin plastic ssop (7.62 mm (300)) pd17243mc- -5a4 30-pin plastic ssop (7.62 mm (300)) pd17244mc- -5a4 30-pin plastic ssop (7.62 mm (300)) pd17245mc- -5a4 30-pin plastic ssop (7.62 mm (300)) pd17246mc- -5a4 30-pin plastic ssop (7.62 mm (300)) remark indicates rom code suffix.
3 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 differences between pd17246 subseries, pd17236 subseries, and pd17255 subseries (1/2) item pd17246 subseries pd17236 subseries pd17225 subseries rom pd17240: 2,048 16 bits pd17230: 2,048 16 bits pd17225: 2,048 16 bits pd17241: 4,096 16 bits pd17231: 4,096 16 bits pd17226: 4,096 16 bits pd17242: 6,144 16 bits pd17232: 6,144 16 bits pd17227: 6,144 16 bits pd17243: 8,192 16 bits pd17233: 8,192 16 bits pd17228: 8,192 16 bits pd17244: 10,240 16 bits pd17234: 10,240 16 bits pd17245: 12,288 16 bits pd17235: 12,288 16 bits pd17246: 16,384 16 bits pd17236: 16,384 16 bits ram 447 4 bits 223 4 bits 111 4 bits ( pd17225, 17226) 223 4 bits ( pd17227, 17228) ports p0b 0 to p0b 3 : i/o (bit i/o) p0b 0 to p0b 3 : i/o (bit i/o) p0b 0 to p0b 3 : input p0c 0 to p0c 3 : i/o (group i/o) p0c 0 to p0c 3 : i/o (group i/o) p0c 0 to p0c 3 : output p0d 0 to p0d 3 : i/o (group i/o) p0d 0 to p0d 3 : i/o (group i/o) p0d 0 to p0d 3 : output p1a 0 to p1a 2 : i/o (bit i/o) p1a 0 : input or output p1b 0 : i/o, functions selectable by mask alternately as int pin option reset the reset pin is internally pulled down by the occurrence of a low level is output from the reset by watchdog the internal reset signals on the left, causing a reset (usually, wdout pin by the timer the reset pin is pulled up). occurrence of the internal reset by stack pointer reset signals on the left, and low-voltage detector a reset takes place if the (mask option) wdout pin is externally connected to the reset pin. capacitor for oscillation selected by mask option not provided (15 pf) vector address basic interval timer: 0002h basic interval timer: 0001h rising and falling rising and falling edges of int pin: 0002h edges of int pin: 0003h 8-bit timer: 0003h 8-bit timer: 0004h ram retention flag provided not provided
4 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 differences between pd17246 subseries, pd17236 subseries, and pd17255 subseries (2/2) item pd17246 subseries pd17236 subseries pd17225 subseries stop mode release <1> when any of pins p0a 0 <1> when any of pins p0a 0 when any of pins p0a 0 to condition to p0a 3 goes low to p0a 3 goes low p0a 3 and p0b 0 to p0b 3 goes <2> when pins p0b 0 to p0b 3 , <2> when pins p0b 0 to p0b 3 , low p0c 0 to p0c 3 , and p0d 0 p0c 0 to p0c 3 , and p0d 0 to p0d 3 are used as input to p0d 3 are used as pins and when any of input pins and when any them goes low of them goes low <3> when an interrupt <3> when an interrupt request (irq) of the request (irq) of the interrupt for which the ip interrupt for which the ip flag is set is generated at flag is set is generated the rising edge or falling at the rising edge or edge of the int pin falling edge of the int <4> when p0e 0 to p0e 3 are pin used as input pins when a key matrix is used and when any of these pins goes low <5> when p1a 0 to p1a 2 and p1b 0 are used as input pins when a key matrix is used and when the level of any of these pins equals the set clear level carrier frequency selected by register file selected by mask option 7.8 khz to 1 mhz (f x = 4 mhz) (after reset: f x /2) <1> if carrier generation <1> if carrier generation clock clock is f x /2: 7.8 khz to is f x /2: 3.9 khz to 1 mhz 1 mhz <2> if carrier generation clock <2> if carrier generation is f x : 7.8 khz to 2 mhz clock is f x : 15.6 khz to <3> if carrier generation clock 2 mhz is 2f x : 15.6 khz to 4 mhz nrz low-level period nrzltmm: 8 bits nrzltmm: 7 bits (bit 7 is rem output control bit) setting modulo register (rem output control bit is bit nrzhtmm: 7 bits (bit 7 is fixed to 0) (nrzltmm) and nrz 1 of register file at address high-level period setting 12h) modulo register nrzhtmm: 8 bits (nrzhtmm)
5 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 pin configuration (top view) 30-pin plastic ssop (7.62 mm (300)) pd17240mc- -5a4, 17241mc- -5a4, 17242mc- -5a4, 17243mc- -5a4, pd17244mc- -5a4, 17245mc- -5a4, 17246mc- -5a4 p0d 2 p0d 3 p1b 0 /int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset p1a 0 p1a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p1a 2 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 gnd: ground int: external interrupt request signal input p0a 0 to p0a 3 : input port (cmos input with pull-up resistor) p0b 0 to p0b 3 : i/o port (cmos input with pull-up resistor/n-ch open-drain output) p0c 0 to p0c 3 : i/o port (cmos input with pull-up resistor/n-ch open-drain output) p0d 0 to p0d 3 : i/o port (cmos input with pull-up resistor/n-ch open-drain output) p0e 0 to p0e 3 : i/o port (when key matrix is used: cmos input with pull-up resistor/n-ch open- drain output, when key matrix is not used: cmos input/push-pull output) p1a 0 /p1a 2 : input port (when key matrix is used: cmos input/n-ch open-drain output, when key matrix is not used: cmos input/push-pull output) p1b 0 : input port (cmos input) rem: remote controller output (cmos push-pull output) reset: reset input v dd : power supply x in , x out : resonator connection
6 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 block diagram p0a 0 p0a 1 p0a 2 p0a 3 p0a p0b 0 p0b 1 p0b 2 p0b 3 p0b p0c 0 p0c 1 p0c 2 p0c 3 p0c p0d 0 p0d 1 p0d 2 p0d 3 p0d p0e 0 p0e 1 p0e 2 p0e 3 p0e p1a 0 p1a 1 p1a 2 p1b 0 p1a p1b rf system registers alu osc cpu clock rem int/p1b 0 v dd gnd x in x out instruction decoder power supply circuit remote control divider 8-bit timer interrupt controller reset reset controller program counter stack (5 levels) ram 447 4 bits rom pd17240: 2,048 16 bits pd17241: 4,096 16 bits pd17242: 6,144 16 bits pd17243: 8,192 16 bits pd17244: 10,240 16 bits pd17245: 12,288 16 bits pd17246: 16,384 16 bits basic interval/ watchdog timer
7 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 contents 1. pin functions .......................................................................................................................... 9 1.1 pin function list ............................................................................................................... 9 1.2 i/o circuits ......................................................................................................................... 12 1.3 handling of unused pins ................................................................................................. 14 2. memory space ......................................................................................................................... 15 2.1 program counter (pc) ...................................................................................................... 15 2.2 program memory (rom) .................................................................................................. 18 2.3 stack ............................................................................................................................... .... 20 2.4 data memory (ram) .......................................................................................................... 22 2.5 register file (rf) .............................................................................................................. 31 3. ports ........................................................................................................................ .................. 34 3.1 port 0a (p0a 0 to p0a 3 ) ..................................................................................................... 34 3.2 port 0b (p0b 0 to p0b 3 ) ..................................................................................................... 34 3.3 port 0c (p0c 0 to p0c 3 ) ..................................................................................................... 34 3.4 port 0d (p0d 0 to p0d 3 ) ..................................................................................................... 34 3.5 port 0e (p0e 0 to p0e 3 ) ...................................................................................................... 35 3.6 port 1a (p1a 0 to p1a 2 ) ..................................................................................................... 35 3.7 port 1b (p1b 0 ).................................................................................................................... 36 3.8 int pin ............................................................................................................................... .37 3.9 switching bit i/o (port 0b, 0e, 1a) ................................................................................. 38 3.10 selecting i/o mode of group i/o (port 0c, 0d) ............................................................. 40 3.11 selecting whether key matrix is used or not (port 0e, 1a) ....................................... 41 3.12 specifying resistor connection (port 0e, 1a) ............................................................. 42 3.13 selecting standby mode release condition and whether pull-up or pull-down resistor is connected (port 1a) ..................................................................................... 44 3.14 selecting whether key matrix is used, standby mode release condition, and whether pull-up or pull-down resistor is connected (port 1b) ............................... 46 4. clock generator ................................................................................................................. 47 4.1 instruction execution time (cpu clock) selection ...................................................... 47 5. 8-bit timer and remote controller carrier generator ................................... 48 5.1 configuration of 8-bit timer (with modulo function) .................................................. 48 5.2 function of 8-bit timer (with modulo function) .......................................................... 50 5.3 carrier generator for remote controller ....................................................................... 51 6. basic interval timer/watchdog timer ......................................................................... 57 6.1 source clock for basic interval timer ........................................................................... 57 6.2 controlling basic interval timer ..................................................................................... 57 6.3 operation timing for watchdog timer ........................................................................... 59 7. ram retention detector ................................................................................................... 60 7.1 ram retention flag .......................................................................................................... 60
8 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8. interrupt functions ........................................................................................................... 62 8.1 interrupt sources .............................................................................................................. 62 8.2 hardware of interrupt controller .................................................................................... 63 8.3 interrupt sequence ........................................................................................................... 66 9. standby functions ............................................................................................................... 68 9.1 halt mode ......................................................................................................................... 68 9.2 halt instruction execution conditions ........................................................................ 69 9.3 stop mode ........................................................................................................................ 70 9.4 stop instruction execution conditions ........................................................................ 71 9.5 releasing standby mode ................................................................................................. 72 10. reset ............................................................................................................................... ........... 73 10.1 reset by reset signal input ............................................................................................ 73 10.2 reset by watchdog timer (with reset pin internally pulled down) ........................ 73 10.3 reset by stack pointer (with reset pin internally pulled down) ............................. 74 11. low-voltage detector (with reset pin internally pulled down) ................. 75 12. assembler reserved words ............................................................................................ 76 12.1 mask option directives .................................................................................................... 76 12.2 reserved symbols ............................................................................................................ 77 13. instruction set ..................................................................................................................... 83 13.1 instruction set outline ..................................................................................................... 83 13.2 legend ............................................................................................................................... .84 13.3 list of instructions ........................................................................................................... 85 13.4 assembler (ra17k) embedded macro instructions .................................................... 87 14. electrical specifications ................................................................................................ 88 15. application circuit example ........................................................................................... 94 16. package drawing ................................................................................................................. 95 17. recommended soldering conditions ........................................................................ 96 appendix a differences between pd17246 and pd17p246 ....................................... 97 appendix b development tools ............................................................................................ 98
9 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 1. pin functions 1.1 pin function list (1/3) pin no. pin name function output format after reset 28 p0d 0 these pins constitute a 4-bit i/o port which can be set to the input n-ch low-level 29 p0d 1 or output mode in 4-bit units (group i/o). open drain output 1 p0d 2 in the input mode, these pins serve as cmos input pins with a 2 p0d 3 pull-up resistor, and can be used to input the key return signals of a key matrix. the standby status must be released when at least one of the input lines goes low. in the output mode, these pins are used as n-ch open-drain output pins and can be used to output the signals of a key matrix. 3 p1b 0 /int this is an input port pin. whether this pin functions as the p1b 0 p1b 0 input pin or the int pin can be selected by the register file. (when key p1b 0 matrix not this is a 1-bit cmos input port. used and no this port can be used to input key return signals when a key resistor matrix is used. at this time, whether a pull-up/down resistor is connected) connected to this port and the standby mode release condition (whether it is released when this pin is high or low) can be selected. 1. if connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes low ... a pull-up resistor is connected. if a low level is input to the p1b 0 pin, the standby mode is released. 2. if connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes high ... a pull-down resistor is connected. if a high level is input to the p1b 0 pin, the standby mode is released. 3. if connection of a resistor is not specified and if it is specified that the standby mode is released when this pin goes low (or high) ... no resistor is connected. if a low (or high) level is input to the p1b 0 pin, the standby mode is released. if a key matrix is not used, whether a resistor is connected and whether the resistor is pull-up or pull-down can be selected. int this is an external interrupt request signal. it can also be used to release the standby mode if an external interrupt request signal is input to this pin while the int pin interrupt enable flag (ip) is set.
10 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 1.1 pin function list (2/3) pin no. pin name function output format after reset 4 p0e 0 these pins constitute a 4-bit i/o port that can be set to the input or when key cmos input 5 p0e 1 output mode in 1-bit units. matrix is (when key 6 p0e 2 if this port is set to the input mode when a key matrix is used, it used: n-ch matrix is not 7 p0e 3 functions as a cmos input port with a pull-up resistor and can be open-drain, used and no used to input key return signals. if one of the pins of this port when key resistor goes low, the standby mode is released. matrix is not connected) if this port is set to the output mode when a key matrix is used, it used: cmos functions as an n-ch open-drain output port and can be used to push-pull output key matrix signals. if this port is set to the input mode when a key matrix is not used, it functions as a cmos input port to/from which a resistor can be connected/disconnected in 1-bit units. if this port is set in the output mode when a key matrix is not used, it functions as a high- current cmos output port. 8 rem outputs transfer signal for infrared remote controller. cmos low-level active-high output. push-pull output 9v dd power supply 10 x out connects ceramic resonator for system clock oscillation. (oscillation 11 x in a capacitor (15 pf) for oscillation can be connected by using a stops) mask option. 12 gnd ground 13 reset system reset input. turns on pull down resistor if the poc or input watchdog timer overflows and if the stack pointer overflows or underflows, and resets the system. usually, the pull-down resistor is on.
11 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 1.1 pin function list (3/3) pin no. pin name function output format after reset 14 p1a 0 these pins constitute a 3-bit i/o port that can be set to the input or when key cmos input 15 p1a 1 output mode in 1-bit units. matrix is (when key 30 p1a 2 if this port is set to the input mode when a key matrix is used, it used: n-ch matrix is not functions as a cmos input port and can be used to input key open-drain, used and return signals. at this time, whether a pull-up/down resistor is when key no resistor connected to this port and the standby mode release condition matrix is not connected) (whether it is released when this pin is high or low) can be used: cmos selected in 1-bit units push-pull. 1. if connection of a resistor is specified and if it is specified that the standby mode is released when this port goes low ... a pull-up resistor is connected. if a low level is input to the set key, the standby mode is released. 2. if connection of a resistor is specified and if it is specified that the standby mode is released when this port goes high ... a pull-down resistor is connected. if a high level is input to the set key, the standby mode is released. 3. if connection of a resistor is not specified and if it is specified that the standby mode is released when this port goes low (or high) ... no resistor is connected. if a low (or high) level is input to the set key, the standby mode is released. if this port is set to the output mode when a key matrix is used, it functions as an n-ch open-drain output port and can be used to output key matrix signals. if this port is set to the input mode when a key matrix is used, it functions as a cmos input port. connection of a resistor to this port and whether the resistor is pull-up or pull-down can be selected in 1-bit units. if this port is set in the output mode when a key matrix is not used, it functions as a high-current cmos output port. 16 p0a 0 these pins are cmos input pins with a 4-bit pull-up resistor. cmos input 17 p0a 1 they can be used to input the key return signals of a key matrix. with pull-up 18 p0a 2 if any one of these pins goes low, the standby status is released. resistor 19 p0a 3 20 p0b 0 these pins constitute a 4-bit i/o port that can be set to the input or n-ch cmos input 21 p0b 1 output mode in 1-bit units. open drain with pull-up 22 p0b 2 in the input mode, these pins are cmos input pins with a pull-up resistor 23 p0b 3 resistor, and can be used to input the key return signals of a key matrix. the standby status is released when at least one of these pins goes low. in the output mode, they serve as n-ch open-drain output pins and can be used to output the key return signals of a key matrix. 24 p0c 0 these pins constitute a 4-bit i/o port that can be set to the input or n-ch low-level 25 p0c 1 output mode in 4-bit units (group i/o). open drain output 26 p0c 2 in the input mode, these pins are cmos input pins with a pull-up 27 p0c 3 resistor, and can be used to input the key return signals of a key matrix. the standby status is released when at least one of these pins goes low. in the output mode, they serve as n-ch open-drain output pins and can be used to output the key return signals of a key matrix.
12 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 1.2 i/o circuits the equivalent i/o circuit for each pd17246 pin is shown below. figure 1-1. i/o circuits (1/2) (1) p0a v dd input buffer (2) p0b, p0c, p0d v dd p-ch n-ch output latch selector data output disable input buffer (3) p0e p-ch p-ch n-ch pull-up resistor output latch input buffer data data data output disable selector v dd v dd key matrix use/non- use resistor (4) p1a p-ch n-ch key matrix use/non- use resistor pull-up/ pull-down resistor output latch stop clear level input buffer data data data data output disable selector p-ch n-ch v dd v dd (5) p1b p-ch n-ch v dd data data stop clear level selector input buffer pull-up/ pull-down resistor
13 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (6) reset v dd p-ch reset input n-ch input buffer schmitt trigger input with hysteresis characteristics (7) int input buffer schmitt trigger input with hysteresis characteristics (8) rem data p-ch n-ch v dd output disable figure 1-1. i/o circuits (2/2)
14 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 1.3 handling of unused pins handle the unused pins as follows. table 1-1. handling of unused pins pin name recommended connection p0a 0 to p0a 3 leave open. p0b 0 to p0b 3 p0c 0 to p0c 3 p0d 0 to p0d 3 p0e 0 to p0e 3 connect to gnd (when input). p1a 0 to p1a 2 p1b 0 /int connect to gnd. rem leave open.
15 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2. memory space 2.1 program counter (pc) the program counter (pc) specifies an address of the program memory (rom). the program counter consists of an 11/12/13-bit binary counter and a 1-bit segment register (sgr) as shown in figure 2-1. its contents are initialized to address 0000h at reset. figure 2-1. configuration of program counter page pc ( pd17240) msb lsb sgr pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc ( pd17241) pc ( pd17242, 17243) pc ( pd17244, 17245, 17246) 2.1.1 segment register (sgr) the segment register specifies a segment of the program memory. table 2-1 shows the relationship between the segment register and program memory. table 2-1. relationship between segment register and program memory value of segment register segment of program memory 0 segment 0 1 segment 1 the segment register is set when the following instructions are executed. br @ar call @ar syscal entry
16 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 page 1 page 2 page 3 page 0 (16 bits 2k steps) (16 bits 8k steps) segment 0 page 1 page 2 page 3 (16 bits 8k steps) segment 1 (system segment) block 0 block 1 block 2 block 7 block 0 of segment 1 entry address of syscal instruction 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 7 f 7 f 8 0 8 0 f f f f 0 0 0 0 f f f f 0 0 0 0 h h h h h h h h 0 0 0 0 0 0 0 0 2 2 3 3 2 3 3 2 7 f 7 f 8 0 8 0 f f f f 0 0 0 0 f f f f 0 0 0 0 h h h h h h h h 020ffh 02100h 021ffh 02200h 022ffh 02700h 02000h 0200fh area in which entry address of system segment can be specified . . . . the first address of the subroutine that can be called by the system call instruction ( syscal entry ) is the first 16 steps of each block (blocks 0 to 7) in page 0 of segment 1 (system segment). figure 2-2. outline of system call instruction
17 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 contents of program counter (pc) note sgr 1 0 0 b 12 0 0 1 1 0 0 0 b 11 0 1 0 1 0 0 0 b 10 0 b 9 0 b 8 0 b 7 0 0 b 6 0 0 b 5 0 0 b 4 0 0 b 3 0 b 2 0 b 1 0 b 0 0 program counter instruction br addr call addr syscal entry br @ar call @ar movt dbf, @ar ret retsk reti other instructions (including skip instruction) on acknowledging interrupt watchdog timer reset, reset pin, reset by stack pointer page 0 page 1 page 2 page 3 entry l entry h operand of instruction (addr) operand of instruction (addr) contents of address register re- tained re- tained contents (return address) of address stack register (asr) specified by stack pointer (sp) vector address of each interrupt increment re- tained figure 2-3. value of program counter on execution of each instruction note pd17240: b 0 to b 10 pd17241: b 0 to b 11 pd17242, 17243: b 0 to b 12 pd17244, 17245, 17246: b 0 to b 12 , sgr remark entry h : higher 3 bits of entry entry l : lower 4 bits of entry table 2-2. interrupt vector address priority internal/external interrupt source vector address 1 internal 8-bit timer 0004h 2 external rising and falling edges of int pin 0003h 3 internal basic interval timer 0002h
18 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.2 program memory (rom) the configuration of the program memory is as follows. part number program memory capacity program memory address pd17240 2,048 16 bits 0000h to 07ffh pd17241 4,096 16 bits 0000h to 0fffh pd17242 6,144 16 bits 0000h to 17ffh pd17243 8,192 16 bits 0000h to 1fffh pd17244 10,240 16 bits 0000h to 27ffh pd17245 12,288 16 bits 0000h to 2fffh pd17246 16,384 16 bits 0000h to 3fffh the program memory stores the program, interrupt vector table, and fixed data table. the program memory is addressed by the program counter. figure 2-4 shows the program memory map. the entire range of the program memory can be addressed by the bd addr, br @ar, call @ar, movt dbf, and @ar instructions. note, however, that the subroutine entry addresses that can be specified by the call addr instruction are from 0000h to 07ffh.
19 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 figure 2-4. program memory map ( pd17246) 16 bits h h branch addresses for br addr instruction branch addresses for br@ar instruction subroutine entry addresses for call@ar instruction table reference addresses for movt dbf, @ar instruction address h h h h h h h h h ( pd17245) reset start address basic interval timer interrupt vector int pin rising/falling edge interrupt vector 8-bit timer interrupt vector segment 0 page 0 page 1 page 2 page 3 page 0 page 1 page 2 page 3 subroutine entry address for call addr instruction subroutine entry address for call addr instruction branch addresses for br addr instruction segment 1 (system segment) 0 f 2 3 4 f f f f 0 f 0 f 0 0 0 f f f f 0 f 0 f 0 0 0 7 f 7 f 0 f 0 3 0 h normal address 1 0 0 0 0 0 0 0 1 1 2 2 h f f 7 2 ( pd17240) ( pd17241) ( pd17242) ( pd17243) ( pd17244)
20 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.3 stack a stack is a register used to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is acknowledged. 2.3.1 stack configuration figure 2-5 shows the stack configuration. a stack consists of a stack pointer (a 4-bit binary counter, the highest bit fixed to 0), five 11-bit ( pd17240)/12- bit ( pd17241)/13-bit ( pd17242, 17243)/14-bit ( pd17244, 17245, 17246) address stack registers, and three 6- bit interrupt stack registers. figure 2-5. stack configuration address stack registers (asr) b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address stack register 1 address stack register 2 address stack register 3 address stack register 4 b 2 b 1 b 0 spb 2 spb 1 spb 0 stack pointer (sp) 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h interrupt stack registers (intsk) banksk1 banksk2 bcdsk0 bcdsk1 bcdsk2 cmpsk0 cmpsk1 cmpsk2 cysk0 cysk1 cysk2 zsk0 zsk1 zsk2 ixesk0 ixesk1 ixesk2 address stack register 0 the reset pin is internally pulled down and reset is effected. b 3 0 b 12 pd17241 pd17242, 17243 pd17244, 17245, 17246 b 4 b 3 b 2 b 5 banksk0 b 1 b 0 undefined undefined undefined b 13 pd17240
21 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.3.2 function of stack the address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is acknowledged. it also stores the contents of the address registers (ars) when a stack manipulation instruction (push ar) is executed. if subroutines or interrupts are nested to more than 5 levels, the reset pin is internally pulled down and a reset is effected. the interrupt stack register (intsk) saves the contents of the bank register (bank) and program status word (psword) when an interrupt is acknowledged. the saved contents are restored when an interrupt return (reti) instruction is executed. intsk saves data each time an interrupt is acknowledged, but the data stored first is lost if more than 3 levels of interrupts occur . 2.3.3 stack pointer (sp) and interrupt stack pointer table 2-3 shows the operations of the stack pointer (sp). the stack pointer can take eight values, 0h to 7h. because there are only five stack registers available, however, the reset pin is internally pulled down and reset is effected if the value of sp is 6 or greater . table 2-3. operations of stack pointer instruction value of stack pointer (sp) counter of interrupt stack register call addr ? 10 call @ar movt dbf, @ar (1st instruction cycle) push ar syscal entry when interrupt is acknowledged 1 1 ret +1 0 retsk movt dbf, @ar (2nd instruction cycle) pop ar reti +1 +1
22 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4 data memory (ram) the data memory (ram) stores data for operations and control. it can always be read/written by instructions. 2.4.1 memory configuration figure 2-6 shows the configuration of the data memory (ram). the data memory consists of four banks : bank0, bank1, bank2, and bank3. in each bank, every 4 bits of data are assigned an address. the higher 3 bits of the address indicate a row address and the lower 4 bits of the address indicate a column address . for example, a data memory location indicated by row address 1h and column address 0ah is termed a data memory location at address 1ah. each address stores data of 4 bits (= 1 nibble). in addition, the data memory is divided into the following six functional blocks. (1) system register (sysreg) a system register (sysreg) is resident on addresses 74h to 7fh (12 nibbles) of each bank. in other words, each bank has the same system register at its addresses 74h to 7fh. (2) data buffer (dbf) a data buffer is resident on addresses 0ch to 0fh (4 nibbles) of bank 0 of the data memory. the reset value is 0320h. (3) general register (gr) a general register is resident on any row (16 nibbles) of any bank of the data memory. the row address of the general register is pointed to by the general register pointer (rp) in the system register (sysreg). (4) port register a port data register is resident on addresses 6fh, and 70h to 73h of bank0 and addresses 70h and 71h of bank1 (7 nibbles) of the data memory. no data can be written to or read from addresses 72h and 73h of bank1 and addresses 70h to 73h of bank2 or bank3.
23 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (5) general-purpose data memory the general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. this memory area has a total of 447 nibbles (111 nibbles in bank0 and 336 nibbles (112 nibbles 3) in bank1 to bank3). figure 2-6. configuration of data memory (1/2) notes 1. address 6fh of bank1 can be used as a general-purpose data memory area. 2. bits 0 to 2 of address 70h of bank1 are used. bit 3 is fixed to 0. 3. only bit 0 of address 71h of bank1 is used. bits 1 to 3 are fixed to 0. caution no data can be written to or read from addresses 72h and 73h of bank1. 0123456789abcdef 0 1 2 3 4 5 6 7 bank 0 0123456789abcdef bank 1 system register (sysreg) example address 1ah in bank 0 system register (sysreg) row address row address column address data buffer (dbf) p0a p0b p0c p0d p0e column address 0 1 2 3 4 5 6 7 p1a note 2 note 1 p1b note 3
24 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 figure 2-6. configuration of data memory (2/2) 0123456789abcdef 0 1 2 3 4 5 6 row address column address bank2 system register (sysreg) note 0123456789abcdef 0 1 2 3 4 5 6 row address column address bank3 system register (sysreg) note note address 6fh of bank2, bank3 can be used as a general-purpose data memory area. caution no data can be written to or read from addresses 70h to 73h of bank2 and bank3.
25 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4.2 system registers (sysreg) the system registers are registers that are directly related to control of the cpu. these registers are mapped to addresses 74h to 7fh on the data memory and can be referenced regardless of bank specification. the system registers include the following registers. address registers (ar0 to ar3) window register (wr) bank register (bank) memory pointer enable flag (mpe) memory pointers (mph, mpl) index registers (ixh, ixm, ixl) general register pointers (rph, rpl) program status word (psword) figure 2-7. configuration of system registers b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ar 3 ar 2 ar 1 ar 0 wr bank ixh ixm ixl rph rpl psw mph mpl address register (ar) window register (wr) bank register (bank) data memory row address pointer (mp) index register (ix) general register pointer (rp) program status word (psword) 000 00 00 00 m p e b c d c m p c yz i x e (rp) (ix) (mp) (bank) data bit symbol name address initial value at reset 0000000000000000 0000000000000000000000000000 undefined (wr) (ar) ( pd17242,17243) (ar) ( pd17241) (ar) ( pd17240) 00000 0000 00 (ar) ( pd17244,17245,17246)
26 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4.3 general register (gr) a general register is a register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) configuration of general register figure 2-8 shows the configuration of the general registers. a general register occupies 16 nibbles (16 4 bits) on a selected row address of the data memory as shown in figure 2-8. the row address is selected by the general register pointer (rp) of the system register. five bits of rp are valid. of these, the lower 3 bits (bits 1 to 3 of rpl) are used to set a row address, and the higher 2 bits (bits 0 and 1 of rph) are used to set a bank. the data memory that can be used as general registers is at row addresses 0h to 7h in bank0 to 4. (2) functions of general registers a general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. as a general register is a part of the data memory, you can say that the general registers enable arithmetic operations and data transfer between two locations of the data memory. similarly, the general registers can be accessed by a data memory manipulation instruction as they are a part of the data memory.
27 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 figure 2-8. configuration of general registers general register pointer (rp) rph 0123456789abcdef rpl bank0 column address bank1 system register general register (16 nibbles) port register port register system register rp port register example general registers when rp = 0000010b same system registers exist bank2 system register bank3 system register b 3 b 2 b 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b 3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b 2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 b 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 setting of bank setting of row address general register settable range fixed to 0 fixed to 0 assigned to bcd flag
28 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.4.4 data buffer (dbf) the data buffer on addresses 0ch to 0fh of the data memory is used for data transfer to and from peripheral hardware and for storage of data during table referencing. (1) functions of the data buffer the data buffer has two major functions: a function to transfer data to and from hardware and a function to read constant data from the program memory (for table referencing). figure 2-9 shows the relationship between the data buffer and peripheral hardware. figure 2-9. data buffer and peripheral hardware data buffer (dbf) internal bus program memory (rom) constant data peripheral address peripheral hardware 8-bit timer (tmc, tmm) carrier generator for remote controller (nrzltmm, nrzhtmm) address register (ar) 05h, 06h 03h, 04h 40h
29 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 table 2-4. relationship between peripheral hardware and data buffer peripheral peripheral register transferring data with data buffer hardware name symbol peripheral address data buffer used put/get 8-bit timer 8-bit counter tmc 05h dbf0, dbf1 get only 8-bit modulo tmm 06h dbf0, dbf1 put only register remote controller nrz low-level nrzltmm 03h dbf0, dbf1 put carrier generator timer modulo get register nrz high-level nrzhtmm 04h dbf0, dbf1 put timer modulo get register address register address register ar 40h dbf0 to dbf3 put note 1 get note 2 notes 1. in the pd17240: bits 0 to 3 of ar3 and bit 3 of ar2 are arbitrary values in the pd17241: bits 0 to 3 of ar3 are arbitrary values in the pd17242, 17243: bits 1 to 3 of ar3 are arbitrary values in the pd17244, 17245, 17246: bits 2 to 3 of ar3 are arbitrary values 2. in the pd17240: bits 0 to 3 of ar3 and bit 3 of ar2 are always 0 in the pd17241: bits 0 to 3 of ar3 are always 0 in the pd17242, 17243: bits 1 to 3 of ar3 are always 0 in the pd17244, 17245, 17246: bits 2 to 3 of ar3 are always 0 (2) table referencing an movt instruction reads constant data from a specified location of the program memory (rom) and sets it in the data buffer. the function of the movt instruction is explained below. movt dbf, @ar: reads data from a program memory location pointed to by the address register (ar) and sets it in the data buffer (dbf). dbf 3 dbf 2 dbf 1 dbf 0 movt dbf, @ ar b 15 b 0 16 bits program memory (rom) data buffer
30 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (3) notes on using data buffer when transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing put), and read-only peripheral registers (only when executing get) must be handled as follows. when device operates nothing changes even if data is written to a read-only register. if an unused address is read, an undefined value is read. nothing changes even if data is written to that address. using assembler an error occurs if an instruction is executed to read a write-only register. again, an error occurs if an instruction is executed to write data to a read-only register. an error also occurs if an instruction is executed to read or write an unused address. if an in-circuit emulator (ie-17k or ie-17k-et) is used (when an instruction is executed for patch processing) an undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. nothing changes even if data is written to a read-only register, and an error does not occur. an undefined value is read if an unused address is read; nothing changes even if data is written to this address. an error does not occur.
31 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.5 register file (rf) the register file mainly consists of registers that set the conditions of the peripheral hardware. these registers can be controlled by the dedicated instructions peek and poke, and the embedded macro instructions of ra17k, setn, clrn, and initflg. 2.5.1 configuration of register file figure 2-10 shows the configuration of the register file and how the register file is accessed by the peek and poke instructions. the control registers are controlled by using dedicated instructions peek and poke. since the control registers are assigned to addresses 00h to 3fh regardless of the bank, the addresses 00h to 3fh of the general-purpose data memory cannot be accessed when the peek or poke instruction is used. the addresses that can be accessed by the peek and poke instructions are addresses 00h to 3fh of the control registers and 40h to 7fh of the general-purpose data memory. the register file consists of these addresses. the control registers are assigned to addresses 80h to bfh on the ie-17k to facilitate debugging. figure 2-10. register file configuration and register file access with peek or poke instructions 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address data memory system register 0 1 2 3 peek wr, sp poke lcdmd, wr poke m063, wr control register register file
32 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 2.5.2 control registers the control registers consist of a total of 64 nibbles (64 4 bits) of addresses 00h to 3fh of the register file. of these, however, only 24 nibbles are actually used. the remaining 40 nibbles are unused registers that are prohibited from being read or written. when the peek wr, rf instruction is executed, the contents of the register file addressed by rf are read to the window register. when the poke rf, wr instruction is executed, the contents of the window register are written to the register file addressed by rf . when using the assembler (ra17k), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. the macro instructions allow the contents of the register file to be manipulated in bit units. for the configuration of the control register, refer to figure 12-1 register file list . setn: sets flag to 1 clrn: sets flag to 0 sktn: skips if all flags are 1 skfn: skips if all flags are 0 notn: inverts flag initflg: initializes flag initflgx: initializes flag 2.5.3 notes on using register files when using the register files, bear in mind the points described below. for details, refer to the pd172xx subseries user? manual (u12795e) . (1) when manipulating control registers (read-only and unused registers) when manipulating the write-only (w), the read-only (r), and unused control registers by using an assembler or in-circuit emulator, keep in mind the following points. when device operates nothing changes even if data is written to a read-only register. if an unused register is read, an undefined value is read; nothing is changed even if data is written to this register. using assembler an error occurs if an instruction is executed to read data from a write-only register. an error occurs if an instruction is executed to write data to a read-only register. an error also occurs if an instruction is executed to read or write an unused address. when an in-circuit emulator (ie-17k or ie-17k-et) is used (when an instruction is executed for patch processing) an undefined value is read if a write-only register is read, and an error does not occur. nothing changes even if data is written to a read-only register, and an error does not occur. an undefined value is read if an unused address is read; nothing changes even if data is written to this address. an error does not occur.
33 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) symbol definition of register file an error occurs if a register file address is directly specified as a numeral by the operand rf of the peek wr, rf or poke rf, wr instruction if the 17k series assembler (ra17k) is being used. therefore, the addresses of the register file must be defined in advance as symbols. to define the addresses of the control registers as symbols, define them as addresses 80h to bfh of bank0. the portion of the register file overlapping the data memory (40h to 7fh), however, can be defined as symbols as is.
34 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3. ports 3.1 port 0a (p0a 0 to p0a 3 ) this is a 4-bit input port. data is read using port register p0a (address 70h of bank0). this port is a cmos input port with a pull-up resistor, and can be used as the key return input lines of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. 3.2 port 0b (p0b 0 to p0b 3 ) this is a 4-bit i/o port which can be set to the input or output mode in 1-bit units by using p0bbio (address 26h) of the register file. in the input mode, each bit of this port serves as a cmos input pin with a pull-up resistor and can be used as a key return input line of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. in the output mode, these pins serve as n-ch open-drain output pins and can be used as the key source lines of a key matrix. the data input to this port can be read or the data output from this port can be set by using the p0b register (address 71h of bank0). when this port is read in the output mode, the contents of the output latch are read. in the input mode, a pull-up resistor of 200 k ? is connected to each bit of this port. in the output mode, the pull- up resistor is disconnected. after reset, this port is set to the input mode. 3.3 port 0c (p0c 0 to p0c 3 ) this is a 4-bit i/o port which can be set to the input or output mode in 4-bit units (group i/o) by using p0cdgio (bit 2 of address 37h) of the register file. in the input mode, each bit of this port serves as a cmos input pin with a pull-up resistor and can be used as a key return input line of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. in the output mode, these pins serve as n-ch open-drain output pins and can be used as the key source lines of a key matrix. the data input to this port can be read or the data output from this port can be set by using the p0c register (address 72h of bank0). when this port is read in the output mode, the contents of the output latch are read. in the input mode, a pull-up resistor of 200 k ? is connected to each bit of this port. in the output mode, the pull- up resistor is disconnected. after reset, this port is set to the output mode and outputs a low level. 3.4 port 0d (p0d 0 to p0d 3 ) this is a 4-bit i/o port which can be set to the input or output mode in 4-bit units (group i/o) by using p0cdgio (bit 3 of address 37h) of the register file. in the input mode, each bit of this port serves as a cmos input pin with a pull-up resistor and can be used as a key return input line of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. in the output mode, these pins serve as n-ch open-drain output pins and can be used as the key source lines of a key matrix. the data input to this port can be read or the data output from this port can be set by using the p0d register (address 73h of bank0). when this port is read in the output mode, the contents of the output latch are read. in the input mode, a pull-up resistor of 200 k ? is connected to each bit of this port. in the output mode, the pull- up resistor is disconnected. after reset, this port is set to the output mode and outputs a low level.
35 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.5 port 0e (p0e 0 to p0e 3 ) this is a 4-bit i/o port. the input mode or output mode and whether a key matrix is used or not can be set for this port in 1-bit units. the input and output modes of this port are selected by using p0ebio (address 27h) of the register file. whether a key matrix is used or not is specified by p0ekey (address 16h) of the register file. if this port is set to the input mode when a key matrix is used, it functions as a cmos input port with a pull-up resistor and can be used to input key return signals. if one of the pins of this port goes low, the standby mode is released. if this port is set to the output mode when a key matrix is used, it functions as an n-ch open-drain output port and can be used to output key matrix signals. if this port is set to the input mode when a key matrix is not used, it functions as a cmos input port to/from which a pull-up resistor can be connected/disconnected in 1-bit units, by using p0ebpu (address 17h) of the register file (if a pull-up resistor is connected, it is not disconnected even if the output mode is set). at this time, the standby mode is not released. if this port is set to the output mode when a key matrix is not used, it functions as a high-current cmos output port. to read the input data from this port or set output data to it, use the p0e register (address 6fh of bank0). when this port is read in the output mode, the contents of the output latch are read. after reset, this port is set to the input mode (a key matrix is not used and a resistor is not connected). 3.6 port 1a (p1a 0 to p1a 2 ) these pins constitute a 3-bit i/o port that can be set in the input or output mode in 1-bit units. if this port is set to the input mode when a key matrix is used, it functions as a cmos input port and can be used to input key return signals. at this time, whether a resistor is connected to this port and the standby mode release condition (whether it is released when this port is high or low) can be selected. 1. if connection of a resistor is specified and if it is specified that the standby mode is released when this port goes low ... a pull-up resistor is connected. if a low level is input to the set key, the standby mode is released. 2. if connection of a resistor is specified and if it is specified that the standby mode is released when this port goes high ... a pull-down resistor is connected. if a high level is input to the set key, the standby mode is released. 3. if connection of a resistor is not specified and if it is specified that the standby mode is released when this port goes low (or high) ... no resistor is connected. if a low (or high) level is input to the set key, the standby mode is released. if this port is set to the output mode when a key matrix is used, it functions as an n-ch open-drain output port and can be used to output key matrix signals. if this port is set to the input mode when a key matrix is not used, it functions as a cmos input port. connection of a resistor to this port and whether a pull-up or pull-down resistor is connected to the port can be selected in 1-bit units. at this time, the standby mode is not released. if this port is set to the output mode when a key matrix is not used, it functions as a high-current cmos output port. to set this port to the input mode or output mode, use p1abio (address 25h) of the register file. to specify whether a key matrix is used or not, use p1akey (address 06h) of the register file. to specify whether a resistor is connected, use p1abpu (address 07h) of the register file. to specify the standby mode release condition (to specify whether a pull-down or pull-up resistor is connected when a key matrix is not used), use p1ahl (address 05h) of the register file. use the p1a register (address 70h of bank1) to read the input data from this port or set output data to it. when this port is read in the output mode, the contents of the output latch are read. after reset, this port is set to the input mode (a key matrix is not used and a resistor is not connected).
36 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.7 port 1b (p1b 0 ) the p1b 0 pin functions alternately as the int pin. to use the p1b 0 pin, set intsel (bit 1 of address 1fh) of the register file to 0. the p1b 0 pin functions as a 1-bit cmos input port. this port can be used to input a key return signal when a key matrix is used. at this time, whether a resistor is connected to this port and the standby mode release condition (whether it is released when this pin is high or low) can be selected. 1. if connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes low ... a pull-up resistor is connected. if a low level is input to p1b 0 , the standby mode is released. 2. if connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes high ... a pull-down resistor is connected. if a high level is input to p1b 0 , the standby mode is released. 3. if connection of a resistor is not specified and if it is specified that the standby mode is released when this pin goes low (or high) ... no resistor is connected. if a low (or high) level is input to p1b 0 , the standby mode is released. if a key matrix is not used, whether a resistor is connected and whether a pull-up or pull-down resistor is connected can be selected. at this time, the standby mode is not released. to specify whether a resistor is connected, use p1bpu0 (bit 0 of address 05h) of the register file. to specify whether a key matrix is used or not, use p1bkey0 (bit 1 of address 05h) of the register file. to specify a standby condition (to specify whether a pull-down or pull-up resistor is connected when a key matrix is not used), use p1bhl0 (bit 2 of address 05h) of the register file. use the p1b register (address 71h of bank1) to read the input data. after reset, the p1b 0 pin is selected and functions as an input port (a key matrix is not used and a resistor is not connected).
37 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.8 int pin the int pin functions alternately as the p1b 0 pin. to use the int pin, set intsel (bit 1 of address 1fh) of the register file to 1. this pin inputs an external interrupt request signal. the irq flag (rf: bit 0 of address 3eh) is set at either the rising or falling edge of the signal input to this pin. the status of this pin can be read by using the int flag (rf: bit 0 of address 0fh). when a high level is input to the pin, the int flag is set to ?? when a low level is input, the flag is reset to ??(refer to 8.2.1 int ). table 3-1. relationship between port register and each pin bank address target port bit output read contents written contents after reset format input mode output mode input mode output mode 0 70h port 0a b 3 p0a3 input pin status input mode b 2 p0a2 (with pull-up b 1 p0a1 resistor) b 0 p0a0 71h port 0b b 3 p0b3 n-ch output latch output latch output latch b 2 p0b2 open drain b 1 p0b1 b 0 p0b0 72h port 0c b 3 p0c3 output mode b 2 p0c2 (low-level b 1 p0c1 output) b 0 p0c0 73h port 0d b 3 p0d3 b 2 p0d2 b 1 p0d1 b 0 p0d0 6fh port 0e b 3 p0e3 cmos b 2 p0e2 push-pull b 1 p0e1 or n-ch b 0 p0e0 open drain 1 70h port 1a b 2 p1a2 cmos b 1 p1a1 push-pull b 0 p1a0 or n-ch open drain 71h port 1b b 0 p1b0 input input mode (when key matrix not used and no resistor connected) input mode (when key matrix not used and no pull-up resistor connected) input mode (when key matrix not used and no resistor connected)
38 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.9 switching bit i/o (port 0b, 0e, 1a) an i/o that can be set to the input or output mode in bit units is called a bit i/o. p0b, p0e, and p1a are bit i/o ports, which can be set in the input or output mode in bit units by the register file shown below. when the mode is changed from input to output, the p0b, p0e, and p1a output latch contents are output to the port lines as soon as the mode has been changed. 3210 p0bbio3 p0bbio2 p0bbio1 p0bbio0 address rf: 26h after reset 0h r/w r/w p0bbio0 0 1 sets p0b 0 input/output mode p0bbio1 0 1 sets p0b 1 input/output mode p0bbio2 0 1 sets p0b 2 input/output mode p0bbio3 0 1 sets p0b 3 input/output mode sets p0b 0 in input mode sets p0b 0 in output mode sets p0b 1 in input mode sets p0b 1 in output mode sets p0b 2 in input mode sets p0b 2 in output mode sets p0b 3 in input mode sets p0b 3 in output mode
39 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 32 10 p0ebio3 p0ebio2 p0ebio1 p0ebio0 address rf: 27h p0ebio0 after reset 0h r/w r/w 0 1 sets p0e 0 input/output mode sets p0e 0 in input mode sets p0e 0 in output mode p0ebio1 0 1 p0ebio2 0 1 p0ebio3 0 1 sets p0e 1 input/output mode sets p0e 1 in input mode sets p0e 1 in output mode sets p0e 2 input/output mode sets p0e 2 in input mode sets p0e 2 in output mode sets p0e 3 input/output mode sets p0e 3 in input mode sets p0e 3 in output mode p1abio0 0 1 0 p1abio0 address rf: 25h after reset 0h r/w r/w 1 p1abio1 2 p1abio2 3 0 sets p1a 0 input/output mode p1abio1 0 1 sets p1a 1 input/output mode p1abio2 0 1 sets p1a 2 input/output mode sets p1a 0 in input mode sets p1a 0 in output mode sets p1a 1 in input mode sets p1a 1 in output mode sets p1a 2 in input mode sets p1a 2 in output mode
40 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.10 selecting i/o mode of group i/o (port 0c, 0d) an i/o that is set to the input or output mode in 4-bit units is called a group i/o. p0c and p0d can be used as group i/o ports. the input and output modes of these ports are selected by using the following register file. if the mode is changed from input to output, the contents of the port register are output to the respective ports as soon as the mode has been changed. 3210 p0dgio p0cgio 0 0 address rf: 37h after reset ch r/w r/w p0cgio 0 1 i/o mode of p0c 0 to p0c 3 p0dgio 0 1 i/o mode of p0d 0 to p0d 3 sets p0c 0 to p0c 3 in input mode sets p0c 0 to p0c 3 in output mode sets p0d 0 to p0d 3 in input mode sets p0d 0 to p0d 3 in output mode
41 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.11 selecting whether key matrix is used or not (port 0e, 1a) by using the following register file, whether p0e and p1a are used for a key matrix can be selected in bit units. p1akey0 0 1 0 p1akey0 address rf: 06h after reset 0h r/w r/w 1 p1akey1 2 p1akey2 3 0 selects whether p1a 0 is used for key matrix or not p1akey1 0 1 selects whether p1a 1 is used for key matrix or not p1akey2 0 1 selects whether p1a 2 is used for key matrix or not p1a 0 not used for key matrix p1a 0 used for key matrix p1a 2 not used for key matrix p1a 2 used for key matrix p1a 1 not used for key matrix p1a 1 used for key matrix p0ekey0 0 1 0 p0ekey0 address rf: 16h after reset 0h r/w r/w 1 p0ekey1 2 p0ekey2 3 p0ekey3 selects whether p0e 0 is used for key matrix or not p0ekey1 0 1 selects whether p0e 1 is used for key matrix or not p0ekey2 0 1 selects whether p0e 2 is used for key matrix or not p0ekey3 0 1 selects whether p0e 3 is used for key matrix or not p0e 0 not used for key matrix p0e 0 used for key matrix p0e 1 not used for key matrix p0e 1 used for key matrix p0e 2 not used for key matrix p0e 2 used for key matrix p0e 3 not used for key matrix p0e 3 used for key matrix
42 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.12 specifying resistor connection (port 0e, 1a) (1) port 0e if a key matrix is not used, whether or not a pull-up resistor is connected to port p0e can be specified in 1- bit units by using the following registers of the register file note . 32 10 p0ebpu3 p0ebpu2 p0ebpu1 p0ebpu0 address rf: 17h p0ebpu0 after reset 0h r/w r/w 0 1 connects pull-up resistor to p0e 0 p0ebpu1 0 1 p0ebpu2 0 1 p0ebpu3 0 1 not connected connected connects pull-up resistor to p0e 1 not connected connected connects pull-up resistor to p0e 2 not connected connected connects pull-up resistor to p0e 3 not connected connected note to disconnect the pull-up resistor in the output mode, clear the corresponding bit of the p0ebpu register.
43 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) port 1a whether a resistor is connected to each bit of port p1a when a key matrix is not used can be specified in 1- bit units by using the following register file note . to connect a resistor, select whether a pull-down or pull-up resistor is to be connected, by using p1ahl (address 05h) of the register file. p1abpu0 0 1 0 p1abpu0 address rf: 07h after reset 0h r/w r/w 1 p1abpu1 2 p1abpu2 3 0 connects resistor to p1a 0 p1abpu1 0 1 connects resistor to p1a 1 p1abpu2 0 1 connects resistor to p1a 2 not connected connected not connected connected not connected connected note to disconnect the resistor in the output mode, clear the corresponding bit of the p1abpu register.
44 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 3.13 selecting standby mode release condition and whether pull-up or pull-down resistor is connected (port 1a) the standby mode release condition and whether a pull-up or pull-down resistor note is connected to p1a can be specified in 1-bit units by using the following register file. note specify whether a resistor is connected or not by using p1abpu (address 07h) of the register file. (1) when key matrix is used (p1akeyn = 1) p1ahl0 0 1 0 p1ahl0 address rf: 05h after reset 0h r/w r/w 1 p1ahl1 2 p1ahl2 3 0 resistor is connected (p1abpu0 = 1) resistor is not connected (p1abpu0 = 0) connects pull-down/pull-up resistor to p1a 0 and selects standby mode release condition pull-up resistor standby mode is released when a low level is input to p1a. pull-down resistor standby mode is released when a high level is input to p1a. no resistor no resistor p1ahl1 0 1 resistor is connected (p1abpu1 = 1) resistor is not connected (p1abpu1 = 0) connects pull-down/pull-up resistor to p1a 1 and selects standby mode release condition pull-up resistor standby mode is released when a low level is input to p1a. pull-down resistor standby mode is released when a high level is input to p1a. no resistor no resistor p1ahl2 0 1 resistor is connected (p1abpu2 = 1) resistor is not connected (p1abpu2 = 0) connects pull-down/pull-up resistor to p1a 2 and selects standby mode release condition pull-up resistor standby mode is released when a low level is input to p1a. pull-down resistor standby mode is released when a high level is input to p1a. no resistor no resistor remark p1akey: address 06h of register file p1abpu: address 07h of register file n = 0 to 2
45 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (2) when key matrix is not used (p1akeyn = 0) p1ahl0 0 1 0 p1ahl0 address rf: 05h after reset 0h r/w r/w 1 p1ahl1 2 p1ahl2 3 0 resistor is connected (p1abpu0 = 1) resistor is not connected (p1abpu0 = 0) connects pull-down/pull-up resistor to p1a 0 pull-up resistor pull-down resistor no resistor p1ahl1 0 1 resistor is connected (p1abpu1 = 1) resistor is not connected (p1abpu1 = 0) connects pull-down/pull-up resistor to p1a 1 pull-up resistor pull-down resistor no resistor p1ahl2 0 1 resistor is connected (p1abpu2 = 1) resistor is not connected (p1abpu2 = 0) connects pull-down/pull-up resistor to p1a 2 pull-up resistor pull-down resistor no resistor caution the standby mode is not released by p1a when a key matrix is not used. remark p1akey: address 06h of register file p1abpu: address 07h of register file n = 0 to 2
46 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 0 p1bpu0 address rf: 15h after reset 0h r/w r/w 1 p1bkey0 2 p1bhl0 3 0 p1bhl0 0 1 resistor is connected (p1bpu0 = 1) resistor is not connected (p1bpu0 = 0) connects pull-down/pull-up resistor to p1b 0 pull-up resistor pull-down resistor no resistor p1bpu0 0 1 connects resistor to p1b 0 p1bkey0 0 1 selects whether p1b 0 is used for key matrix or not ? when key matrix is used (p1bkey0 = 1) p1bhl0 0 1 resistor is connected (p1bpu0 = 1) resistor is not connected (p1bpu0 = 0) connects pull-down/pull-up resistor to p1b 0 and selects standby mode release condition pull-up resistor standby mode is released when a low level is input to p1b. pull-down resistor standby mode is released when a high level is input to p1b. no resistor no resistor ? when key matrix is not used (p1bkey0 = 0) p1b 0 not used for key matrix p1b 0 used for key matrix not connected connected 3.14 selecting whether key matrix is used, standby mode release condition, and whether pull-up or pull-down resistor is connected (port 1b) whether a key matrix is used or not, whether a resistor is connected to p1b or not, whether a pull-up or pull-down resistor is connected, and the standby mode release condition can be specified by using the following register file. caution the standby mode is not released by p1b when a key matrix is not used.
47 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 4. clock generator 4.1 instruction execution time (cpu clock) selection the pd17246 is equipped with a clock oscillator that supplies clocks to the cpu and peripheral hardware. instruction execution time can be changed in two steps (normal mode and high-speed mode) without changing the oscillation frequency. to change the instruction execution time, change the mode of sysck (rf: address 02h) of the register file by using the poke instruction. note, that the mode is actually only changed when the instruction next to the poke instruction has been executed. when using the high-speed mode, pay attention to the supply voltage. (refer to 14. electrical specifications .) after reset, the normal mode is set. 32 10 0 0 0 sysck address rf: 02h sysck after reset 0h r/w r/w 0 1 selects instruction execution time normal mode 32/f x (8 s) high-speed mode 16/f x (4 s) values in parentheses apply to operation when the system clock f x = 4 mhz.
48 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 5. 8-bit timer and remote controller carrier generator the pd17246 is equipped with an 8-bit timer, which is mainly used to generate the leader pulse of the remote controller signal and to output codes. 5.1 configuration of 8-bit timer (with modulo function) figure 5-1 shows the configuration of the 8-bit timer. as shown in this figure, the 8-bit timer consists of an 8-bit counter (tmc), an 8-bit modulo register (tmm), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. to start/stop the 8-bit timer, and to reset the 8-bit counter, tmen (address 33h, bit 3) and tmres (address 33h, bit 2) of the register file are used. to select the operation clock of the 8-bit timer, use tmck1 (address 33h, bit 1) and tmck0 (address 33h, bit 0) of the register file. the value of the 8-bit counter is read by using the get instruction through the dbf (data buffer). no value can be set to the 8-bit counter. a value is set to the modulo register by using the put instruction through dbf. the value of the modulo register cannot be read. when the value of the counter matches with that of the modulo register, an interrupt flag (irqtm: address 3fh, bit 0) of the register file is set. tmc 76543210 address after reset r/w peripheral register: 05h 00h r 8-bit counter tmm address after reset r/w peripheral register: 06h ffh w 76543210 8-bit modulo register caution do not clear tmm to 0 (irqtm is not set).
49 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 figure 5-1. configuration of 8-bit timer and remote controller carrier generator remark tmm, tmc, nrzltmm, and nrzhtmm are peripheral registers. data buffer internal bus rf: 33h f x /32 sw f x /64 f x /256 q r s tmen tmres tmck1 tmck0 8-bit modulo register tmm 8-bit counter tmc 8-bit counter rf: 11h rf: 12h comparator nrzbf nrz rem 8-bit modulo register nrzltmm 8-bit counter comparator 8-bit modulo register nrzhtmm comparator irqtm 8-bit timer remote controller carrier generator selector f x /2 f x 2f x remen rf: 12h
50 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 5.2 function of 8-bit timer (with modulo function) notes 1. when the stop mode is released, bit 3 must be set. 2. bit 2 is a write-only bit. caution if the system clock is changed while the timer is counting, an error occurs in the timer as follows (when system clock f x = 4 mhz): high-speed mode 16/f x normal mode 32/f x ... (error due to resolution of set timer) +1.5 s normal mode 32/f x high-speed mode 16/f x ... (error due to resolution of set timer) ?.5 s 32 10 tmen tmres tmck1 tmck0 address rf: 33h tmres after reset 8h note 1 r/w r/w note 2 0 1 8-bit timer reset flag data read out is always "0" resets 8-bit counter and irqtm tmen 0 1 8-bit timer count enable flag stops 8-bit timer count operation enables 8-bit timer count operation (falling edge) tmck1 tmck0 00 01 10 11 8-bit timer clock source selection count clock: f x /32 (measurable time range: 8 s to 2.048 ms, resolution: 8 s (error: +8 s)) count clock: f x /64 (measurable time range: 16 s to 4.096 ms, resolution: 16 s (error: +16 s)) count clock: f x /256 (measurable time range: 64 s to 16.384 ms, resolution: 64 s (error: +64 s)) remote controller carrier generator output values in parentheses apply to operation when system clock f x = 4 mhz. ?
51 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 5.3 carrier generator for remote controller pd17246 is provided with a carrier generator for the remote controller. the remote controller carrier generator consists of an 8-bit counter, nrz high-level timer modulo register (nrzhtmm), and nrz low-level timer modulo register (nrzltmm). the high-level and low-level periods are set in the corresponding modulo registers through the dbf to determine the carrier duty factor and carrier frequency. as a clock input to the 8-bit counter, f x /2, f x , or 2f x can be selected by using remck0 and remck1 (address 13h, bits 0 and 1) of the register file (this clock for carrier generation is rf x ). when rf x is oscillated by a 4 mhz resonator, therefore, the input clock is 2 mhz (f x /2), 4 mhz (f x ), or 8 mhz (2f x ). the nrz high-level output timer modulo register is called nrzhtmm, and the nrz low-level timer modulo register is called nrzltmm. data is written to these registers by the put instruction. the contents in these register are read by the get instruction. whether the rem pin outputs a carrier or a high level is selected by remen (address 12h, bit 1) of the register file. be sure to clear this bit to 0 to output a carrier. nrzltmm 0 1 2 3 8-bit modulo register 4 5 6 address peripheral register: 03h after reset undefined r/w r/w 7 nrzhtmm remck1 0 0 1 1 remck0 0 1 0 1 0 remck0 address rf: 13h after reset 0h r/w r/w 1 remck1 2 0 3 0 rf x = f x /2 (when f x = 4 mhz, rf x = 2 mhz) rf x = f x (when f x = 4 mhz, rfx = 4 mhz) rf x = 2f x note (when f x = 4 mhz, rf x = 8 mhz) 0 1 2 3 8-bit modulo register 4 5 6 address peripheral register: 03h after reset undefined r/w r/w 7 clock for carrier generation (rf x ) note rf x = 2f x can be selected only when f x = 3.5 to 4.5 mhz.
52 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 5.3.1 remote controller signal output control the rem pin, which outputs the carrier, is controlled by bits nrz and nrzbf of the register file and timer 0. while the nrz contents are 1 , the clock generated by the remote controller carrier generator is output to the rem pin; while the nrz contents are 0 , the rem pin outputs a low level. the nrzbf contents are automatically transferred to nrz by the interrupt signal generated by timer 0. if data is set in nrzbf in advance, the rem pin status changes in synchronization with the timer 0 counting operation. if the interrupt signal is generated from timer 0 with the rem pin at the high level (i.e. nrz is 1 ) and the carrier clock at the high level, the rem pin output does not accord with the updated contents of nrz until the carrier clock goes low. this processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). when the contents of nrz are 0 , the remote controller carrier generator stops. however, if the clock for timer 0 is output from the remote controller carrier generator, the clock continues to operate, even when the nrz contents become 0 . an actual example showing a remote controller signal output to the rem pin is given below. when remen (address 12h, bit 1) of register file is 0 (carrier output) nrz rem max. 500 ns (delay) note (f x = 4 mhz, rf x = f x /2) rem pin does not go low until carrier goes low even if nrz becomes 0 note value when (tmck1, tmck0) (1, 1). when (tmck1, tmck0) = (1, 1), the value differs depending on how nrz is manipulated. if nrz is set by an instruction, the width of the first high-level pulse may be shortened. if nrz is set by data transferred from nrzbf, the high-level pulse is delayed by the low-level pulse of the carrier clock.
53 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 when remen (address 12h, bit 1) of register file is 1 (carrier not output) nrz rem 0 nrz address rf: 12h after reset 0h r/w r/w 1 remen 2 0 3 0 remen 0 0 1 1 nrz 0 1 0 1 nrz data 0 nrzbf address rf: 11h after reset 0h r/w r/w 1 0 2 0 3 0 nrzbf 0 1 nrz data output next outputs low level to rem pin outputs a carrier to rem pin outputs low level to rem pin outputs high level to rem pin nrz buffer bit. transferred to nrz by interrupt signal of timer 0.
54 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 . . . . setting carrier frequency and duty factor where the system clock frequency is f x , carrier frequency is f c , and carrier generation clock is rf x : when rf x = f x /2: (division ratio) = f x /(2 f c ) when rf x = f x : (division ratio) = f x /f c when rf x = 2f x : (division ratio) = 2f x /f c is divided into m:n and is set in the modulo registers as follows: high-level period set value = { m/(m + n)} 1 low-level period set value = { n/(m + n)} 1 example where f c = 38 khz, duty factor (high-level period) = 1/3, f x = 4 mhz, and rf x = 2f x : = 2 4 mhz/38 khz = 210.5 m:n = 1:2 from the above, the value of the modulo register is: high-level period = 69 low-level period = 139 therefore, the carrier frequency is 38.10 khz. table 5-1. carrier frequency list (1) where f x = 4 mhz and rf x = f x /2 set value t h ( s) t l ( s) 1/f c ( s) f c (khz) duty nrzhtmm nrzltmm 00h 00h 0.5 0.5 1.0 1000 1/2 01h 02h 1.0 1.5 2.5 400 2/5 04h 04h 2.5 2.5 5.0 200 1/2 09h 09h 5.0 5.0 10.0 100 1/2 0fh 10h 8.0 8.5 16.5 60.6 1/2 0fh 21h 8.0 17.0 25.0 40.0 1/3 11h 21h 9.0 17.0 26.0 38.5 1/3 11h 22h 9.0 17.5 26.5 37.7 1/3 19h 35h 13.0 27.0 40.0 25.0 1/3 3fh 3fh 32.0 32.0 64.0 15.6 1/2 7fh 7fh 64.0 64.0 128.0 7.8 1/2 ffh ffh 128.0 128.0 256.0 3.9 1/2
55 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 rem (f c ) t h t l 1/f c (2) where f x = 4 mhz, rf x = f x (original oscillation) set value t h ( s) t l ( s) 1/f c ( s) f c (khz) duty nrzhtmm nrzltmm 00h 00h 0.25 0.25 0.5 2000 1/2 01h 02h 0.5 0.75 1.25 800 2/5 04h 04h 1.25 1.25 2.5 400 1/2 09h 09h 2.5 2.5 5.0 200 1/2 0fh 10h 4.0 4.25 8.25 121 1/2 0fh 21h 4.0 8.5 12.5 80 1/3 11h 21h 4.5 8.5 13.0 76.9 1/3 11h 22h 4.5 8.75 13.25 75.47 1/3 19h 35h 6.5 13.5 20.0 50 1/3 3fh 3fh 16.0 16.0 32.0 31.25 1/2 7fh 7fh 32.0 32.0 64.0 15.6 1/2 ffh ffh 64.0 64.0 128.0 7.8 1/2 (3) where f x = 4 mhz, rf x = 2f x set value t h ( s) t l ( s) 1/f c ( s) f c (khz) duty nrzhtmm nrzltmm 00h 00h 0.125 0.125 0.25 4,000 1/2 07h 0bh 1.0 1.5 2.5 400 2/5 13h 13h 2.5 2.5 5.0 200 1/2 27h 27h 5.0 5.0 10 100 1/2 41h 41h 8.25 8.25 16.5 60.6 1/2 41h 85h 8.25 16.75 25 40 1/3 45h 89h 8.75 17.25 26.0 38.5 1/3 45h 8bh 8.75 17.5 26.25 38.10 1/3 69h d5h 13.25 26.75 40.0 25 1/3 c7h c7h 25.0 25.0 50.0 20 1/2 ffh ffh 32.0 32.0 64.0 15.6 1/2
56 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 5.3.2 countermeasures against noise during transmission (carrier output) when a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 a may flow through the infrared led. since two batteries are usually used as the power source of the transmitter, several ? of equivalent resistance (r) exists in the power source as shown in figure 5-2. this resistance increases to 10 to 20 ? if the supply voltage drops to 2 v. while the carrier is being output from the rem pin (while the infrared led lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. to minimize the influence on the microcontroller of this high-frequency noise, take the following measures. <1> separate the power lines of the microcontroller from the power lines of the infrared led with the terminals of the batteries at the center. use thick power lines and keep the wiring short. <2> locate the resonator as close as possible to the microcontroller and shield it with gnd lines (as indicated by the shaded portion in the figure below). <3> locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. also, use a capacitor to eliminate high-frequency noise. <4> to prevent data from changing, do not execute data read/write processing such as key scan, an interrupt that requires a stack, or the call/ret instruction, while the carrier is being output. <5> to improve the reliability in case of program hang-up, use the watchdog timer. figure 5-2. example of countermeasures against noise 0.5 to 1 a infrared led rem v dd microcontroller + r batteries v ss
57 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 6. basic interval timer/watchdog timer the basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 source clock for basic interval timer the system clock (f x ) is divided to generate the source clock for the basic interval timer. the input clock frequency for the basic interval timer is f x /2 7 . when the cpu is set in the stop mode, the basic interval timer also stops. 6.2 controlling basic interval timer the basic interval timer is controlled by the bits in the register file. that is, the basic interval timer is reset by btmres. the frequency for the interrupt signal, output by the basic interval timer, is selected by btmmd, and the watchdog timer is reset by wdtres. figure 6-1. basic interval timer configuration system clock f x 1/2 divider 7 1/2 divider 11 1/2 divider 1/2 divider 1/2 divider btmres wdtres btmck irqbtm reset signal output selector b f x /2 18 f x /2 20
58 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 32 10 wdtres btmck btmres 0 address rf: 03h btmres after reset 0h r/w r/w note 0 1 basic interval timer reset data read out is always "0" writing "1" resets basic interval timer btmck 0 1 basic interval timer mode selection generates interrupt signal irqbtm every f x /2 20 wdtres 0 1 watchdog timer reset data read out is always "0" writing "1" resets watchdog timer (f x /2 21 counter) generates interrupt signal irqbtm every f x /2 18 note bits 1 and 3 are write-only bits.
59 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 6.3 operation timing for watchdog timer the basic interval timer can be used as a watchdog timer. unless the watchdog timer is reset within a fixed time note , it is judged that the program has hung up , and the pd17246 is reset. it is therefore necessary to reset the watchdog timer via programming within the fixed time. the watchdog timer can be reset by setting wdtres to 1. note fixed time: approx. 340 ms (at 4 mhz) caution the watchdog timer cannot be reset in the shaded range in figure 6-2. therefore, set wdtres before both the f x /2 21 and f x /2 20 signals go high. figure 6-2. watchdog timer operation timing f x /2 18 intbtm (f x /2 20 ) intbtm (f x /2 18 ) reset signal wdtres watchdog timer reset signal reset signal goes low if wdtres is not set setting wdtres at this timing is invalid f x /2 19 f x /2 20 f x /2 21
60 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 7. ram retention detector 7.1 ram retention flag the ram retention flag (bit 0 of the register file at address 21h) indicates whether the supply voltage has dropped below the level at which the contents of the ram are lost while the battery is being exchanged or when the battery voltage has dropped. this flag is at bit 3 of control register 0 (p3). it is cleared to 0 if the supply voltage drops below the ram retention detection voltage (approx. 1.4 v typ.). if this flag is 0, it can be judged that the ram contents have been lost or that power has just been applied. this flag can be used to initialize the ram via software. after initializing the ram and writing the necessary data to it, set this ram retention flag to 1 by software. at this time, 1 means that data has been set to the ram. figure 7-1. supply voltage transition and detection voltage v dd v poc v id 0 v ram retention flag (a) (b) (6) (5) (4) (3) (2) set to 1 flag content is read. flag content is read. (1) t poc detection voltage v poc = 1.85 v (typ.) ram retention detection voltage v id = 1.4 v (typ.) (1) if the supply voltage rises after the battery has been set, and exceeds v poc (poc detection voltage), reset is cleared. because the supply voltage rises from 0 v, which is lower than v id (ram retention detection voltage), the ram retention flag remains in the initial status 0. (2) the supply voltage has now risen to the level at which the device can operate. write the necessary data to the ram and set the ram retention flag to 1. (3) the device is reset if the supply voltage drops below v poc . at point (a) in the above figure, the ram retention flag remains 1 because the supply voltage is higher than v id at this point. (4) if the ram retention flag is checked by software after reset has been cleared, it is 1. this means that the contents of the ram have not been lost. it is therefore not necessary to initialize the ram by software. (5) the device is reset if the supply voltage drops below v poc . at point (b) in the figure, the voltage is lower than v id . consequently, the ram retention flag is cleared to 0. (6) if the ram retention flag is checked by software after reset has been cleared, it is 0. this means that the contents of the ram may have been lost. if this happens, initialize the ram by software.
61 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 ramflag 0 1 0 ramflag address rf: 21h after reset undefined note r/w r/w 1 0 2 0 3 0 ram retention flag ram data may be undefined. ram data are retained. note ramflag is 0 when v dd is about 1.4 v or less, and undefined when v dd is about 1.4 v or more.
62 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8. interrupt functions 8.1 interrupt sources pd17246 is provided with three interrupt sources. when an interrupt has been acknowledged, the program execution automatically branches to a predetermined address, which is called a vector address. a vector address is assigned to each interrupt source, as shown in table 8-1. table 8-1. vector address priority interrupt source ext/int vector address 1 8-bit timer internal 0004h 2 int pin rising and falling edges external 0003h 3 basic interval timer internal 0002h remark 0001h is normal address when more than one interrupt request is issued at the same time, the interrupts are acknowledged in sequence, starting from the one with the highest priority. whether an interrupt is enabled or disabled is specified by the ei or di instruction. the basic condition under which an interrupt is acknowledged is that the interrupt is enabled by the ei instruction. while the di instruction is executed, or while an interrupt is acknowledged, the interrupt is disabled. to enable acknowledgement of an interrupt after the interrupt has been processed, the ei instruction must be executed before the reti instruction. acknowledging the interrupt is enabled by the ei instruction after the instruction next to the ei instruction has been executed. therefore, no interrupt can be acknowledged between the ei and reti instructions. caution in interrupt processing, only the bcd, cmp, cy, z, ixe flags are automatically saved to the stack by the hardware, to a maximum of three levels. also, within the interrupt processing contents, when peripheral hardware (timer, a/d converter, etc. ) is accessed, the dbf and wr contents are not saved by the hardware. accordingly, it is recommended that at the beginning of interrupt processing, dbf and wr be saved by software to ram, and immediately before finishing interrupt processing, the saved contents be returned to their original location.
63 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8.2 hardware of interrupt controller this section describes the flags of the interrupt controller. (1) interrupt request flag and interrupt enable flag the interrupt request flag (irq ) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is executed. an interrupt enable flag (ip ) is provided for each interrupt request flag. when the ip flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) ei/di instruction whether an acknowledged interrupt is executed or not is specified by the ei or di instruction. when the ei instruction is executed, inte (interrupt enable flag), which enables the interrupt, is set to 1. the inte flag is not registered on the register file. consequently, the status of this flag cannot be checked by an instruction. the di flag clears the inte flag to 0 to disable all the interrupts. the inte flag is also cleared to 0 at reset, disabling all the interrupts. table 8-2. interrupt request flags and interrupt enable flag interrupt signal setting interrupt request flag interrupt request flag enable flag irqtm reset by 8-bit timer. iptm irq set when edge of int pin input signal is detected ip irqbtm reset by basic interval timer. ipbtm 8.2.1 int this flag reads the int pin status. when a high level is input to the int pin, this flag is set to 1; when a low level is input, the flag is reset to 0. 32 10 0 0 0 int address rf: 0fh int after reset undefined r/w r 0 1 int pin level detection int pin: low level int pin: high level
64 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8.2.2 ieg this pin selects the interrupt edge to be detected on the int pin. when this flag is 0, the interrupt is detected at the rising edge; when it is 1, the interrupt is detected at the falling edge. 8.2.3 intsel this flag selects whether pin 3 is used as the int pin or p1b 0 pin. when intsel is cleared to 0, pin 3 functions as the p1b 0 pin; when it is set to 1, the pin functions as the int pin. after reset, the p1b 0 pin is selected. 321 1 0 address after reset r/w r/w 0h rf: 1fh 00 0 ieg intsel ieg int pin interrupt detection edge selection rising edge of int pin falling edge of int pin 1 0 intsel selection of pin 3 function as p1b 0 pin as int pin 8.2.4 interrupt enable flag this flag enables each interrupt source. when this flag is 1, the corresponding interrupt is enabled; when it is 0, the interrupt is disabled. 32 10 0 ipbtm ip iptm address rf: 2fh iptm after reset 0h r/w r/w 0 1 8-bit timer interrupt enable flag disables interrupt acknowledgement by 8-bit timer enables interrupt acknowledgement by 8-bit timer ip 0 1 int pin interrupt enable flag disables interrupt acknowledgement by int pin input ipbtm 0 1 basic interval timer interrupt enable flag disables interrupt acknowledgement by basic interval timer enables interrupt acknowledgement by basic interval timer enables interrupt acknowledgement by int pin input
65 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8.2.5 irq this is an interrupt request flag that indicates the interrupt request status. when an interrupt request is generated, this flag is set to 1. when the interrupt has been acknowledged, the interrupt request flag is reset to 0. the interrupt request flag can be read or written by the program. therefore, when it is set to 1, an interrupt can be generated by the software. by writing 0 to the flag, the interrupt pending status can be canceled. 32 10 0 0 0 irqbtm address rf: 3dh irqbtm after reset 0h r/w r/w 0 1 basic interval timer interrupt request flag basic interval timer interrupt request has been made. 32 10 0 0 0 irq address rf: 3eh irq after reset 0h r/w r/w 0 1 int pin interrupt request flag interrupt request has not been made. interrupt request has been made at rising edge or falling edge of int input. 32 10 0 0 0 irqtm address rf: 3fh irqtm after reset 1h note r/w r/w 0 1 8-bit timer interrupt request flag 8-bit timer interrupt request has been made. interrupt request has not been made. interrupt request has not been made. note it is also set to 1h after the stop mode is released.
66 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8.3 interrupt sequence if the irq flag is set to 1 when the ip flag is 1 , interrupt processing is started after the instruction cycle of the instruction executed when the irq flag was set has ended. since the movt instruction, ei instruction, and the instruction that matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. if the ip flag is 0 , the interrupt processing is not performed even if the irq flag is set, until the ip flag is set. if two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. the interrupt with the lower priority is held pending until the processing of the interrupt with the higher priority is finished. 8.3.1 operations when interrupt is acknowledged when an interrupt has been acknowledged, the cpu performs processing in the following sequence: clears irq corresponding to inte flag and acknowledged interrupt decrements value of stack pointer by 1 (sp ? 1) saves contents of program counter to stack addressed by stack pointer loads vector address to program counter save contents of psword to interrupt stack register one instruction cycle is required to perform the above processing.
67 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 8.3.2 returning from interrupt processing routine to return from an interrupt processing routine, use the reti instruction. the following processing is then executed within an instruction cycle. loads contents of interrupt stack register to psword increments value of stack pointer by 1 loads contents of stack addressed by stack pointer to program counter to enable an interrupt after the processing of an interrupt has finished, the ei instruction must be executed immediately before the reti instruction. interrupt acknowledgement is enabled by the ei instruction after the instruction next to the ei instruction has been executed. therefore, the interrupt is not acknowledged between the ei and reti instructions.
68 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 9. standby functions the pd17246 is provided with halt and stop modes as standby functions. by using the standby function, current consumption can be reduced. in the halt mode, the program is not executed, but the system clock f x is not stopped. this mode is maintained, until the halt mode release condition is satisfied. in the stop mode, the system clock is stopped and program execution is stopped. this mode is maintained, until the stop mode release condition is satisfied. the halt mode is set, when the halt instruction has been executed. the stop mode is set, when the stop instruction has been executed. 9.1 halt mode in this mode, program execution is temporarily stopped, with the main clock continuing oscillation, to reduce current consumption. use the halt instruction to set the halt mode. the halt mode release condition can be specified by the operand for the halt instruction, as shown in table 9-1. after the halt mode has been released, the operation is performed as shown in table 9-2 and figure 9-1. caution do not execute an instruction that clears the interrupt request flag (irq ) for which the interrupt enable flag (ip ) is set immediately before the halt 8h instruction; otherwise, the halt mode may not be set. table 9-1. halt mode releasing conditions operand value release conditions 0010b (02h) when interrupt request (irqtm) occurs for 8-bit timer 1000b (08h) <1> when interrupt request (irqtm, irqbtm, or irq), whose interrupt enable flag (iptm, ipbtm, or ip) is set, occurs <2> when any of p0a 0 to p0a 3 pins goes low <3> when p0b 0 to p0b 3 , p0c 0 to p0c 3 , and p0d 0 to p0d 3 are used as input pins and any of these goes low <4> if p0e 0 to p0e 3 are used as input pins when a key matrix is used and if any of these pins goes low <5> if p1a 0 to p1a 2 and p1b 0 are used as input pins when a key matrix is used and if the level of any of these pins is the set clear level note other than above setting prohibited note set the clear level by using bits 0 to 2 (p1ahl0 to p1ahl2) of the register file at address 05h, and bit 2 (p1bhl0) at address 15h.
69 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 table 9-2. operations after halt mode release (a) halt 08h halt mode released by: interrupt status interrupt enable flag operations after halt mode release when release condition of p0a 0 don? care don? care instruction next to halt is executed to p0a 3 , p0b 0 to p0b 3 , p0c 0 to p0c 3 , p0d 0 to p0d 3 , p0e 0 to p0e 3 , p1a 0 to p1a 2 , p1b 0 is satisfied when release condition is di disabled standby mode is not released satisfied by interrupt request enabled instruction next to halt is executed ei disabled standby mode is not released enabled branches to interrupt vector address (b) halt 02h halt mode released by: interrupt status interrupt enable flag operations after halt mode release 8-bit timer di disabled instructions are executed from the enabled instruction next to the halt instruction. ei disabled enabled branches to interrupt vector address 9.2 halt instruction execution conditions the halt instruction can be executed under special conditions, as shown in table 9-3, to prevent the program from hanging up. if the conditions in table 9-3 are not satisfied, the halt instruction is treated as a nop instruction. table 9-3. halt instruction execution conditions operand value execution conditions 0010b (02h) when all interrupt request flags (irqtm) of 8-bit timer are reset 1000b (08h) <1> when interrupt request flag (irqth, irqbtm, or irq) is reset, corresponding to interrupt whose interrupt enable flag (iptm, ipbtm, or ip) is set <2> when high level is input to all p0a 0 to p0a 3 pins <3> when p0b 0 to p0b 3 , p0c 0 to p0c 3 , and p0d 0 to p0d 3 are used as input pins, a high level must be input to all the pins. <4> a high level must be input to all the pins if p0e 0 to p0e 3 are used as input pins when a key matrix is used. <5> a level reverse to the set clear level note must be input to all the pins if p1a 0 to p1a 2 and p1b 0 are used as input pins when a key matrix is used (for example, if the clear level is high, the execution condition is low-level input). other than above setting prohibited note set the clear level by using bits 0 to 2 (p1ahl0 to p1ahl2) of the register file at address 05h, and bit 2 (p1bhl0) at address 15h.
70 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 9.3 stop mode in the stop mode, the system clock (f x ) oscillation is stopped and the program execution is stopped to minimize current consumption. to set the stop mode, use the stop instruction. the stop mode release condition can be specified by the stop instruction operand, as shown in table 9-4. after the stop mode has released, the pd17246 performs the following. <1> resets irqtm. <2> starts the basic interval timer and watchdog timer (does not reset). <3> resets and starts the 8-bit timer. <4> executes the instruction next to [stop 8h] when the current value of the 8-bit counter matches the value of the modulo register (irqtm is set). the pd17246 oscillator is stopped when the stop instruction has been executed (i.e., in the stop mode). oscillation is not resumed until the stop mode is released. after the stop mode has been released, the halt mode is set. set the time required to release the halt mode by using the timer with modulo function. the time that elapses from when the stop mode has been released by occurrence of an interrupt until an operation mode is set is shown in the following table. caution do not execute an instruction that clears the interrupt request flag (irq ) for which the interrupt enable flag (ip ) is set immediately before the stop 8h instruction; otherwise, the stop mode may not be set. 8-bit modulo register set value time required to set operation mode (tmm) after stop mode release at 4 mhz 40h 4.160 ms (64 s 65) ffh 16.384 ms (64 s 256) caution to set the time required for an operation mode to be set after the stop mode has been released, make sure that sufficient time is allowed for oscillation to stabilize. remark set the 8-bit modulo timer before executing stop instruction. table 9-4. stop mode release conditions operand value release conditions 1000b (08h) <1> when any of p0a 0 to p0a 3 pins goes low <2> when p0b 0 to p0b 3 , p0c 0 to p0c 3 , and p0d 0 to p0d 3 are used as input pins and any of these goes low <3> if the interrupt request (irq) of an interrupt for which the int pin interrupt enable flag (ip) is set is generated at the rising or falling edge of the int pin <4> if p0e 0 to p0e 3 are used as input pins when a key matrix is used and if any of these pins goes low <5> if p1a 0 to p1a 2 and p1b 0 are used as input pins when a key matrix is used and if the level of any of these pins is the set clear level note other than above setting prohibited note set the clear level by using bits 0 to 2 (p1ahl0 to p1ahl2) of the register file at address 05h, and bit 2 (p1bhl0) at address 15h.
71 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 9.4 stop instruction execution conditions the stop instruction can be executed under special conditions, as shown in table 9-5, to prevent the program from hanging up. if the conditions in table 9-5 are not satisfied, the stop instruction is treated as an nop instruction. table 9-5. stop instruction execution conditions operand value execution conditions 1000b (08h) <1> high level input for all p0a 0 to p0a 3 pins <2> when p0b 0 to p0b 3 , p0c 0 to p0c 3 , and p0d 0 to p0d 3 are used as input pins and all pins are high <3> if the int pin interrupt request flag (irq) for an interrupt for which the int pin interrupt enable flag (ip) is set is reset <4> a high level must be input to all the pins if p0e 0 to p0e 3 are used as input pins when a key matrix is used. <5> a level reverse to the set clear level note must be input to all the pins if p1a 0 to p1a 2 and p1b 0 are used as input pins when a key matrix is used (for example, if the clear level is high, the execution condition is low-level input). other than above setting prohibited note set the clear level by using bits 0 to 2 (p1ahl0 to p1ahl2) of the register file at address 05h, and bit 2 (p1bhl0) at address 15h.
72 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 9.5 releasing standby mode the operations for releasing the stop and halt modes are as shown in figure 9-1. figure 9-1. operations after standby mode release (a) releasing stop mode by interrupt (b) releasing halt mode by interrupt remark the dotted line indicates the operation to be performed when the interrupt request releasing the standby mode has been acknowledged. standby release signal stop instruction wait (time set by tmm) operation mode stop mode halt mode operation mode clock oscillation oscillation stops oscillation halt instruction standby release signal clock operation mode operation mode halt mode oscillation
73 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 10. reset 10.1 reset by reset signal input when a low-level signal of more than 10 s is input to the reset pin, the pd17246 is reset. when the system is reset, the oscillator remains in the halt mode and then enters an operation mode, in the same way as when the stop mode is released. the wait time after the reset signal has been canceled is 16.384 ms (f x = 4 mhz). on power application, input the reset signal at least once because the internal circuitry operations are not stable. when pd17246 is reset, the following initialization takes place. (1) program counter is reset to 0. (2) flags in the register file are initialized to their default values (for the default values, refer to figure 12-1 register files ). (3) the default value (0320h) is written to the data buffer (dbf). (4) the hardware peripherals are initialized. (5) the system clock (f x ) stops oscillation. when the reset pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 mhz) later. figure 10-1. reset operation by reset input reset wait starts from address 0h (about 16 ms at 4 mhz) operation mode or standby mode halt mode operation mode oscillation stops 10.2 reset by watchdog timer (with reset pin internally pulled down) when the watchdog timer operates during program execution, the reset pin is internally pulled down, and the program counter is reset to 0 (normally, the reset pin is pulled up). if the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0h. program so that the watchdog timer is reset at intervals of within 340 ms (at f x = 4 mhz) (set the wdtres flag).
74 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 10.3 reset by stack pointer (with reset pin internally pulled down) when the value of the stack pointer reaches 6h or 7h during program execution, the reset pin is internally pulled down, and the program counter is reset to 0 (normally, the reset pin is pulled up). therefore, if an interrupt or call instruction is executed when the value of the stack pointer is 0 (stack underflow) or if the stack level exceeds 6 as a result of execution of the ret instruction because the correspondence between the call and ret instructions is not established (stack overflow), the program can be restarted from address 0h. table 10-1. status of each hardware after reset hardware reset input in reset input standby mode during operation program counter (pc) 0000h 0000h ports input/output input input output latch 0 0 data memory (ram) general-purpose data memory retains previous undefined (except dbf, port register) status dbf 0320h 0320h system register (sysreg) 0 0 wr retains previous undefined status control registers refer to figure 12-1 register files 8-bit timer counter (tmc) 00h 00h modulo register (tmm) ffh ffh remote controller carrier nrz high-level timer modulo register (nrzhtmm) retains previous undefined generator nrz low-level timer modulo register (nrzltmm) status basic interval timer/watchdog timer counter 00h 00h
75 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 11. low-voltage detector (with reset pin internally pulled down) the reset pin is internally pulled down for initialization (reset) to prevent program hang-up that may take place when the batteries are replaced, if the low-voltage detector detects a low voltage. a drop in the supply voltage is detected if the status in which v dd is about 1.7 to 2.0 v lasts for 1 ms or longer. note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low- voltage condition lasts for less than 1 ms. although the voltage at which the reset function is effected ranges from about 1.7 to 2.0 v, the program counter is prevented from hanging up even if the supply voltage drops until the reset function is effected. note that a resonator may stop oscillating before the reset function is effected if normal operation under the low voltage is not guaranteed. the low-voltage detector can be set arbitrarily by a mask option.
76 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 12. assembler reserved words 12.1 mask option directives when developing the pd17246 program, mask options must be specified by using mask option directives in the program. to select the low-voltage detector and capacitor for oscillation of the pd17246, a mask option must be specified. 12.1.1 option and endop directives the portion of the program enclosed by the option and endop directives is called a mask option definition block. this block is described in the following format. description format: symbol mnemonic operand comment [label: ] option [;comment] : : : endop 12.1.2 mask option definition directives table 12-1 lists the directives that can be used in the mask option definition block. here is an example of mask option definition. description example: symbol mnemonic operand comment option optpoc usepoc ; internal low-voltage detector optcap usecap ; internal capacitor for oscillation endop
77 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 table 12-1. mask option definition directives name directive operands 1st operand 2nd operand 3rd operand 4th operand cap optcap 1 usecap (capacitor for oscillation provided) nousecap (capacitor for oscillation not provided) poc optpoc 1 usepoc (low-voltage detector provided) nousepoc (low-voltage detector not provided) 12.2 reserved symbols the symbols defined by the pd17246 device file are listed in table 12-2. the defined symbols are the following register file names, port names, and peripheral hardware names. 12.2.1 register file the names of the symbols assigned to the register file are defined. these registers are accessed by the peek and poke instructions via the window register (wr). figure 12-1 shows the register file. 12.2.2 registers and ports on data memory the names of the registers assigned to addresses 00h to 7fh on the data memory and the names of ports assigned to address 70h and those that follow, and system register names are defined. figure 12-2 shows the data memory configuration. 12.2.3 peripheral hardware the names of peripheral hardware accessed by the get and put instructions are defined. table 12-3 shows the peripheral hardware.
78 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 table 12-2. reserved symbols (1/3) symbol name attribute value r/w description dbf3 mem 0.0ch r/w bits 15 to 12 of data buffer dbf2 mem 0.0dh r/w bits 11 to 8 of data buffer dbf1 mem 0.0eh r/w bits 7 to 4 of data buffer dbf0 mem 0.0fh r/w bits 3 to 0 of data buffer ar3 mem 0.74h r/w bits 15 to 12 of address register ar2 mem 0.75h r/w bits 11 to 8 of address register ar1 mem 0.76h r/w bits 7 to 4 of address register ar0 mem 0.77h r/w bits 3 to 0 of address register wr mem 0.78h r/w window register bank mem 0.79h r/w bank register ixh mem 0.7ah r/w index register, high mph mem 0.7ah r/w data memory row address pointer, high mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w index register, middle mpl mem 0.7bh r/w data memory row address pointer, low ixl mem 0.7ch r/w index register, low rph mem 0.7dh r/w general register pointer, high rpl mem 0.7eh r/w general register pointer, low psw mem 0.7fh r/w program status word bcd flg 0.7eh.0 r/w bcd flag cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index enable flag p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0d0 flg 0.73h.0 r/w bit 0 of port 0d p0d1 flg 0.73h.1 r/w bit 1 of port 0d p0d2 flg 0.73h.2 r/w bit 2 of port 0d p0d3 flg 0.73h.3 r/w bit 3 of port 0d
79 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 table 12-2. reserved symbols (2/3) symbol name attribute value r/w description p0e0 flg 0.6fh.0 r/w bit 0 of port 0e p0e1 flg 0.6fh.1 r/w bit 1 of port 0e p0e2 flg 0.6fh.2 r/w bit 2 of port 0e p0e3 flg 0.6fh.3 r/w bit 3 of port 0e p1a0 flg 1.70h.0 r/w bit 0 of port 1a p1a1 flg 1.70h.1 r/w bit 1 of port 1a p1a2 flg 1.70h.2 r/w bit 2 of port 1a p1b0 flg 1.71h.0 r/w bit 0 of port 1b sp mem 0.81h r/w stack pointer sysck flg 0.82h.0 r/w system clock select flag wdtres flg 0.83h.3 r/w watchdog timer reset flag btmck flg 0.83h.2 r/w basic interval timer mode select flag btmres flg 0.83h.1 r/w basic interval timer mode reset flag p1ahl0 flg 0.85h.0 r/w p1a 0 port standby clear level select flag p1ahl1 flg 0.85h.1 r/w p1a 1 port standby clear level select flag p1ahl2 flg 0.85h.2 r/w p1a 2 port standby clear level select flag p1akey0 flg 0.86h.0 r/w p1a 0 port key matrix select flag p1akey1 flg 0.86h.1 r/w p1a 1 port key matrix select flag p1akey2 flg 0.86h.2 r/w p1a 2 port key matrix select flag p1abpu0 flg 0.87h.0 r/w p1a 0 port pull-up resistor select flag p1abpu1 flg 0.87h.1 r/w p1a 1 port pull-up resistor select flag p1abpu2 flg 0.87h.2 r/w p1a 2 port pull-up resistor select flag int flg 0.8fh.0 r int pin status flag nrzbf flg 0.91h.0 r/w nrz buffer data flag nrz flg 0.92h.0 r/w nrz data flag remen flg 0.92h.1 r/w carrier output select flag remck1 flg 0.93h.1 r/w carrier generation clock select flag remck0 flg 0.93h.0 r/w carrier generation clock select flag p1bhl0 flg 0.95h.2 r/w p1b 0 port standby clear level select flag p1bkey0 flg 0.95h.1 r/w p1b 0 port key matrix select flag p1bbpu0 flg 0.95h.0 r/w p1b 0 port pull-up resistor select flag p0ekey0 flg 0.96h.0 r/w p1e 0 port key matrix select flag p0ekey1 flg 0.96h.1 r/w p1e 1 port key matrix select flag p0ekey2 flg 0.96h.2 r/w p1e 2 port key matrix select flag p0ekey3 flg 0.96h.3 r/w p1e 3 port key matrix select flag p0ebpu0 flg 0.97h.0 r/w p0e 0 pull-up setting flag p0ebpu1 flg 0.97h.1 r/w p0e 1 pull-up setting flag p0ebpu2 flg 0.97h.2 r/w p0e 2 pull-up setting flag p0ebpu3 flg 0.97h.3 r/w p0e 3 pull-up setting flag intsel flg 0.9fh.1 r/w int select flag
80 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 table 12-2. reserved symbols (3/3) symbol name attribute value r/w description ieg flg 0.9fh.0 r/w int pin interrupt edge flag ramflag flg 0.0a1h.0 r/w ram retention flag p1abio0 flg 0.0a5h.0 r/w p1a 0 i/o select flag p1abio1 flg 0.0a5h.1 r/w p1a 1 i/o select flag p1abio2 flg 0.0a5h.2 r/w p1a 2 i/o select flag p0bbio0 flg 0.0a6h.0 r/w p0b 0 i/o select flag p0bbio1 flg 0.0a6h.1 r/w p0b 1 i/o select flag p0bbio2 flg 0.0a6h.2 r/w p0b 2 i/o select flag p0bbio3 flg 0.0a6h.3 r/w p0b 3 i/o select flag p0ebio0 flg 0.0a7h.0 r/w p0e 0 i/o setting flag p0ebio1 flg 0.0a7h.1 r/w p0e 1 i/o setting flag p0ebio2 flg 0.0a7h.2 r/w p0e 2 i/o setting flag p0ebio3 flg 0.0a7h.3 r/w p0e 3 i/o setting flag ipbtm flg 0.0afh.2 r/w basic interval timer interrupt enable flag ip flg 0.0afh.1 r/w int pin interrupt enable flag iptm flg 0.0afh.0 r/w timer interrupt enable flag tmen flg 0.0b3h.3 r/w timer enable flag tmres flg 0.0b3h.2 r/w timer reset flag tmck1 flg 0.0b3h.1 r/w timer clock flag tmck0 flg 0.0b3h.0 r/w timer clock flag p0cgio flg 0.0b7h.2 r/w p0c 3 to p0c 0 i/o select flag p0dgio flg 0.0b7h.3 r/w p0d 3 to p0d 0 i/o select flag irqbtm flg 0.0bdh.0 r/w basic interval timer interrupt request flag irq flg 0.0beh.0 r/w int pin interrupt request flag irqtm flg 0.0bfh.0 r/w timer interrupt request flag tmc dat 05h r timer count register tmm dat 06h w timer modulo register nrzltmm dat 03h r/w nrz low-level timer modulo register nrzhtmm dat 04h r/w nrz high-level timer modulo register ar dat 40h r/w address register usecap dat 0ff11h capacitor with oscillator is used. nousecap dat 0ff22h capacitor with oscillator is not used. usepoc dat 0ff33h poc circuit is used. nousepoc dat 0ff44h poc circuit is not used. dbf dat 0fh fixed operand value for put, get, movt instruction ix dat 01h fixed operand value for inc instruction ar_epa1 dat 8040h indicates that the epa bit of ar is on.
81 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 figure 12-1. register files (1/2) note after reset figure 12-2. data memory configuration note note note note note note note note bit 3 bit 3 bit 3 bit 3 bit 2 bit 2 bit 2 bit 2 bit 1 bit 1 bit 1 bit 1 bit 0 bit 0 bit 0 bit 0 0 1 2 3 0 column address row address 1 234 567 00 0 0 0 sysck 0 0 sp 0 0 nrzbf 0 remen nrz 0 1 tmen 0 tmres tmck1 tmck0 0 0 0 0 0 0 btmres btmck wdtres 0 p1ahl2 p1ahl1 p1ahl0 0 p1bhl0 p1bkey0 p1bpu0 0 p1abio2 p1abio1 p1abio0 0 0 remck1 remck0 0 0 0 0 0 0 0 ramflag 0 0 0 0 0 p1akey2 p1akey1 p1akey0 p0ekey3 p0ekey2 p0ekey1 p0ekey0 0 p1abpu2 p1abpu1 p1abpu0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 p0ebpu0 p0ebio3 p0ebio2 p0ebio1 p0ebio0 1 1 p0dgio p0cgio 0 0 0 0 0 0 0 p0bbio3 p0bbio2 p0bbio1 p0bbio0 p0ebpu1 p0ebpu2 p0ebpu3 0 1 2 3 4 5 6 7 8 9 a b c d e f ar3 ar2 ar1 ar0 wr bank ixh ixm ixl rph rpl psw p0d 0 to p0d 3 p0e 0 to p0e 3 dbf p0c 0 to p0c 3 p1b 0 p0b 0 to p0b 3 p0a 0 to p0a 3 p1a 0 system register dbf3 dbf2 dbf1 dbf0 0 1 2 3 4 5 6 7 column address row address
82 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 figure 12-1. register files (2/2) note after reset p: when int pin is high level, 1; when int pin is low level, 0. table 12-3. peripheral hardware name address valid bit description tmc 05h 8 timer count register tmm 06h 8 timer modulo register nrzltmm 03h 8 low-level timer modulo register for nrz nrzhtmm 04h 8 high-level timer modulo register for nrz ar 40h 16 address register column address row address 89abcdef bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 p 0 0 0 1 0 0 0 int 0 0 0 irqtm 0 0 intsel ieg 0 ipbtm ip iptm 0 0 0 0 0 0 0 irq 0 0 0 0 0 0 0 irqbtm note note note note note note note note
83 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 13. instruction set 13.1 instruction set outline b 15 01 b 14 to b 11 bin. hex. 0 0 0 0 0 add r, m add m, #n4 0 0 0 1 1 sub r, m sub m, #n4 0 0 1 0 2 addc r, m addc m, #n4 0 0 1 1 3 subc r, m subc m, #n4 0 1 0 0 4 and r, m and m, #n4 0 1 0 1 5 xor r, m xor m, #n4 0 1 1 0 6 or r, m or m, #n4 0 1 1 1 7 inc ar inc ix movt dbf, @ar br @ar call @ar ret syscal entry note retsk ei di reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1 0 0 0 8 ld r, m st m, r 1 0 0 1 9 ske m, #n4 skge m, #n4 1 0 1 0 a mov @r, m mov m, @r 1 0 1 1 b skne m, #n4 sklt m, #n4 1 1 0 0 c br addr (page 0) call addr 1 1 0 1 d br addr (page 1) mov m, #n4 1 1 1 0 e br addr (page 2) skt m, #n 1 1 1 1 f br addr (page 3) skf m, #n note pd17244, 17245, 17246 only
84 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 13.2 legend ar: address register asr: address stack register specified by stack pointer addr: program memory address (lower 11 bits) bank: bank register cmp: compare flag cy: carry flag dbf: data buffer entry: entry address of system segment h: halt releasing condition intef: interrupt enable flag intr: register automatically saved to stack in case of interrupt intsk: interrupt stack register ix: index register mp: data memory row address pointer mpe: memory pointer enable flag m: data memory address specified by m r , m c m r : data memory row address (high) m c : data memory column address (low) n: bit position (4 bits) n4: immediate data (4 bits) page: page (bits 11 and 12 of program counter) pc: program counter p: peripheral address p h : peripheral address (higher 3 bits) p l : peripheral address (lower 4 bits) r: general register column address rf: register file address rf r : register file row address (higher 3 bits) rf c : register file column address (lower 4 bits) sp: stack pointer s: stop releasing condition wr: window register ( ): contents addressed by
85 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 cy (r) b3 (r) b2 (r) b1 (r) b0 13.3 list of instructions group mnemonic operand operation instruction code opcode operand add add r, m (r) (r) + (m) 00000 m r m c r m, #n4 (m) (m) + n4 10000 m r m c n4 addc r, m (r) (r) + (m) + cy 00010 m r m c r m, #n4 (m) (m) + n4 + cy 10010 m r m c n4 inc ar ar ar + 1 00111 000 1001 0000 ix ix ix + 1 00111 000 1000 0000 subtract sub r, m (r) (r) (m) 00001 m r m c r m, #n4 (m) (m) n4 10001 m r m c n4 subc r, m (r) (r) (m) cy 00011 m r m c r m, #n4 (m) (m) n4 cy 10011 m r m c n4 logical or r, m (r) (r) (m) 00110 m r m c r m, #n4 (m) (m) n4 10110 m r m c n4 and r, m (r) (r) (m) 00100 m r m c r m, #n4 (m) (m) n4 10100 m r m c n4 xor r, m (r) (r) ? (m) 00101 m r m c r m, #n4 (m) (m) ? n4 10101 m r m c n4 judge skt m, #n cmp 0, if (m) n = n, then skip 11110 m r m c n skf m, #n cmp 0, if (m) n = 0, then skip 11111 m r m c n compare ske m, #n4 (m) n4, skip if zero 01001 m r m c n4 skne m, #n4 (m) n4, skip if not zero 01011 m r m c n4 skge m, #n4 (m) n4, skip if not borrow 11001 m r m c n4 sklt m, #n4 (m) n4, skip if borrow 11011 m r m c n4 rotate rorc r 00111 000 0111 r transfer ld r, m (r) (m) 01000 m r m c r st m, r (m) (r) 11000 m r m c r mov @r, m if mpe = 1 : (mp, (r)) (m) 01010 m r m c r if mpe = 0 : (bank, m r , (r)) (m) m, @r if mpe = 1 : (m) (mp, (r)) 11010 m r m c r if mpe = 0 : (m) (bank, m r , (r)) m, #n4 (m) n4 11101 m r m c n4 movt dbf, sp sp 1, asr pc, pc ar 00111 000 0001 0000 @ar dbf (pc), pc asr, sp sp + 1
86 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 group mnemonic operand operation instruction code opcode operand transfer push ar sp sp 1, asr ar 00111 000 1101 0000 pop ar ar asr, sp sp + 1 00111 000 1100 0000 peek wr, rf wr (rf) 00111 rf r 0011 rf c poke rf, wr (rf) wr 00111 rf r 0010 rf c get dbf, p (dbf) (p) 00111 p h 1011 p l put p, dbf (p) (dbf) 00111 p h 1010 p l branch br addr note 1 note 1 addr @ar pc ar 00111 000 0100 0000 subroutine call addr sp sp 1, asr pc, 11100 addr pc 10 0 addr, page 0 @ar sp sp 1, asr pc, 00111 000 0101 0000 pc ar syscal note 2 entry sp sp 1, asr pc, sgr 1, 00111 entry h 0000 entry l pc 12,11 0, pc 10 8 entry h , pc 7 4 0, pc 3 0 entry l ret pc asr, sp sp + 1 00111 000 1110 0000 retsk pc asr, sp sp + 1 and skip 00111 001 1110 0000 reti pc asr, intr intsk, sp sp + 1 00111 100 1110 0000 interrupt ei intef 1 00111 000 1111 0000 di intef 0 00111 001 1111 0000 other stop s stop 00111 010 1111 s halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000 notes 1. the operation and operation codes br addr of the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 are as follows. (a) pd17240 operand operation opcode addr pc 10 0 addr 01100 (b) pd17241 operand operation opcode addr pc 10 0 addr, page 0 01100 pc 10 0 addr, page 1 01101 (c) pd17242 operand operation opcode addr pc 10 0 addr, page 0 01100 pc 10 0 addr, page 1 01101 pc 10 0 addr, page 2 01110
87 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 (d) pd17243, 17244, 17245, 17246 operand operation opcode addr pc 10 0 addr, page 0 01100 pc 10 0 addr, page 1 01101 pc 10 0 addr, page 2 01110 pc 10 0 addr, page 3 01111 2. pd17244, 17245, and 17246 only 13.4 assembler (ra17k) embedded macro instructions legend flag n: flg type symbol n: bit number < >: contents in < > can be omitted mnemonic operand operation n embedded sktn flag 1, ...flag n if (flag 1) to (flag n) = all 1 , then skip 1 n 4 macro skfn flag 1, ...flag n if (flag 1) to (flag n) = all 0 , then skip 1 n 4 setn flag 1, ...flag n (flag 1) to (flag n) 11 n 4 clrn flag 1, ...flag n (flag 1) to (flag n) 01 n 4 notn flag 1, ...flag n if (flag n) = 0 , then (flag n) 11 n 4 if (flag n) = 1 , then (flag n) 0 initflg flag 1, if description = not flag n, then (flag n) 01 n 4 < flag n> if description = flag n, then (flag n) 1 bankn (bank) n n = 0, 1 expansion brx label jump label instruction callx function-name call sub-routine initflgx flag 1, if description = not (or inv) n 4 ... flag n flag, (flag) 0 if description = flag, (flag) 1
88 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 14. electrical specifications absolute maximum ratings (t a = 25 c) item symbol conditions ratings unit supply voltage v dd 0.3 to +3.8 v input voltage v i 0.3 to v dd + 0.3 v output voltage v o 0.3 to v dd + 0.3 v output current, high note i oh rem pin peak value 36.0 ma rms value 24.0 ma 1 pin (p0e, p1a pins) peak value 7.5 ma rms value 5.0 ma total of p0e, p1a pins peak value 22.5 ma rms value 15.0 ma output current, low note i ol 1 pin (p0b, p0c, p0d, peak value 7.5 ma p0e, p1a, rem pins) rms value 5.0 ma total of p0b, p0c, p0d, peak value 22.5 ma rem pins rms value 15.0 ma total of p0e, p1a pins peak value 30.0 ma rms value 20.0 ma operating temperature t a 40 to +85 c storage temperature t stg 65 to +150 c power dissipation p d t a = 85 c 180 mw note calculate rms value by this expression: [rms value] = [peak value] caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. duty
89 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 recommended operating ranges (t a = ?0 to +85 c, v dd = 2.0 to 3.6 v) item symbol conditions min. typ. max. unit supply voltage v dd1 f x = 1 mhz high-speed mode 2.0 3.6 v (instruction execution time: 16 s) v dd2 f x = 4 mhz high-speed mode (instruction execution time: 4 s) v dd3 f x = 8 mhz normal mode (instruction execution time: 4 s) v dd4 high-speed mode 2.2 3.6 v (instruction execution time: 2 s) oscillation frequency f x rf x = f x /2 or f x 1.0 4.0 8.0 mhz rf x = 2f x 3.5 4.0 4.5 mhz operating temperature t a ?0 +25 +85 c low-voltage detector note t cy 3.5 32 s (mask option) note reset if the status of v dd = 1.7 to 2.0 v lasts for 1 ms or longer. program hang-up does not occur even if the voltage drops, until the reset function is effected. a resonator may stop oscillating before the reset function is effected if normal operation under the low voltage is not guaranteed. caution design the application circuit so that the reset pin goes low when the supply voltage is less than 2.2 v. remark the region indicated by the broken lines in the above figure is the guaranteed operating range in the high-speed mode. f x vs v dd supply voltage v dd (v) 0.4 2 1 3 4 5 6 7 8 9 10 2 0 2.2 3 3.6 4 (normal mode) system clock f x (mhz) (mh z ) operation guaranteed area
90 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 system clock oscillator characteristics (t a = 40 to +85 c, v dd = 2.0 to 3.6 v) resonator recommended item conditions min. typ. max. unit constants ceramic oscillation frequency 1.0 4.0 8.0 mhz resonator (f x ) note 1 oscillation after v dd reached min. 4 ms stabilization time note 2 in oscillation voltage range notes 1. the oscillation frequency only indicates the oscillator characteristics. 2. the oscillation stabilization time is necessary for oscillation to be stabilized after v dd application or stop mode release. caution when using the system clock oscillator, wire as follows in the area enclosed by the dotted lines in the above figure, to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a large current flows. always make the ground point of the oscillator capacitor the same potential as gnd. do not ground the capacitor to a ground pattern through which a large current flows. do not fetch signals from the oscillator. x in x out
91 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 recommended oscillator constant ceramic resonator (t a = ?0 to +85 c) recommended oscillation frequency manufacturer part number circuit constant (pf) voltage range (v dd ) remarks (mhz) c1 c2 min. max. murata mfg. co., ltd. csbla1m00j58-b0 note 1.0 100 100 1.8 3.6 rd = 3.3 k ? csbfb1m00j58-r1 note cstls2m00g56-b0 note 2.0 rd = 1.0 k ? cstcc2m00g56-r0 note on-chip capacitor cstls3m00g56-b0 note 3.0 rd = 470 ? cstcc3m00g56-r0 note on-chip capacitor cstls4m00g56-b0 4.0 on-chip capacitor cstcr4m00g55-r0 cstls6m00g56-b0 6.0 cstcr6m00g55-r0 cstls8m00g56-b0 8.0 cstcc8m00g56-r0 tdk fcr3.52mc5 3.52 1.8 3.6 on-chip capacitor fcr4.0mc5 4.0 fcr4.0msc5 4.0 fcr6.0mc5 6.0 fcr8.0mc5 8.0 kyocera corp. kbr-2.0ms 2.0 68 68 1.8 3.6 kbr-3.0ms 3.0 47 47 kbr-4.0mke 4.0 on-chip capacitor kbr-4.0mse 33 33 kbr-6.0mkc 6.0 on-chip capacitor kbr-6.0msb 33 33 kbr-8.0mkc 8.0 on-chip capacitor kbr-8.0msb 33 33 note a limiting resistor is required when these ceramic resonators are used (refer to the following figure). when other recommended resonators are used, the limiting resistor is not necessary. caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. the internal operation conditions of the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 must be within the specifications of the dc and ac characteristics. x in x out rd c2 c1
92 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 dc characteristics (t a = ?0 to +85 c, v dd = 2.0 to 3.6 v) item symbol conditions min. typ. max. unit input voltage, high v ihi1 reset, int 0.80v dd v dd v v ih2 p0a, p0b, p0c, p0d 0.70v dd v dd v v ih3 p0e, p1a, p1b 0.70v dd v dd v input voltage, low v il1 reset, int 0 0.2v dd v v il2 p0a, p0b, p0c, p0d 0 0.3v dd v v il3 p0e, p1a, p1b 0 0.3v dd v input leakage current, high i lih p0a, p0b, p0c, p0d, p0e, v ih = v dd 3.0 a p1a, p1b 0 /int, reset w/o pull-down resistor input leakage current, low i lil p0e, p1a, p1b 0 /int v il = 0 v 3.0 a w/o pull-up resistor internal pull-up resistor r 1 p0e, p1a, p1b, reset (pulled up) 25 50 100 k ? r 2 p0a, p0b, p0c, p0d 100 200 400 k ? internal pull-down resistor r 3 p1a, p1b 25 50 100 k ? output current, high i oh rem v oh = 1.0 v, 6 13 24 ma v dd = 3 v output voltage, high v oh p0e, p1a, rem i oh = 0.5 ma v dd 0.3 v dd v output voltage, low v ol1 p0b, p0c, p0d, rem i ol = 0.5 ma 0 0.3 v v ol2 p0e, p1a i ol = 1.5 ma 0 0.3 v data retention characteristics v dddr reset = low level or stop mode 1.3 3.6 v low-voltage detection v dt reset pin pulled down, v dt = v dd 1.85 2.0 v voltage (mask option) ram retention detection v id v id = v dd , ramflag = 0 (rf21h.0) 1.40 1.50 v voltage supply current i dd1 operating mode v dd = 3 v 10% f x = 1 mhz 0.6 1.1 ma (high-speed) f x = 4 mhz 0.75 1.3 ma f x = 8 mhz 0.9 1.6 ma i dd2 operating mode v dd = 3 v 10% f x = 1 mhz 0.48 0.9 ma (low-speed) f x = 4 mhz 0.6 1.1 ma f x = 8 mhz 0.8 1.4 ma i dd3 halt mode v dd = 3 v 10% f x = 1 mhz 0.4 0.75 ma f x = 4 mhz 0.45 0.85 ma f x = 8 mhz 0.5 0.95 ma i dd4 stop mode v dd = 3 v 10% 2.0 20.0 a built-in poc t a = 25 c 2.0 5.0 a note this does not include the current that flows through the internal pull-up resistors.
93 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 ac characteristics (t a = ?0 to +85 c, v dd = 2.0 to 3.6 v) item symbol conditions min. typ. max. unit cpu clock cycle time note t cy1 v dd = 2.0 to 3.6 v 3.4 33 s (instruction execution time) t cy2 v dd = 2.2 to 3.6 v 1.9 33 s int high-/low-level width t inth , 20 s t intl reset low-level width t rsl 10 s note the cpu clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and sysck (rf: address 02h) of the register file. the figure below shows the cpu clock cycle time t cy vs. supply voltage v dd characteristics (refer to 4. clock generator ). t cy vs v dd supply voltage v dd (v) 2 1 3 4 5 6 7 8 9 10 33 40 2 01 3 4 cpu clock cycle time tc y ( s) 3.4 1.9 2.2 3.6 operation guaranteed area
94 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 15. application circuit example 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p1a 2 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 p0d 2 p0d 3 p1b 0 /int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset p1a 0 p1a 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 = jog shuttle 3 v key matrix 8 9 = 72 keys + 4 mhz
95 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 16. package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
96 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 17. recommended soldering conditions the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 17-1. surface mounting type soldering conditions pd17240mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd17241mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd17242mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd17243mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd17244mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd17245mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) pd17246mc- -5a4: 30-pin plastic ssop (7.62 mm (300)) recommended condition soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (at 210 c or higher), count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (at 200 c or higher), count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
97 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 appendix a differences between pd17246 and pd17p246 the pd17p246 is equipped with prom to which data can be written by the user instead of the internal mask rom (program memory) of the pd17246. table a-1 shows the differences between the pd17246 and pd17p246. the cpu functions and internal hardware of the pd17p246, 17240, 17241, 17242, 17243, 17244, 17245, and 17246 are identical. therefore, the pd17p246 can be used to evaluate the program developed for the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 system. note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the pd17p246 differ from those of the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246. table a-1. differences between pd17246 and pd17p246 product name pd17p246 pd17246 item ( pd17p246m1, 17p246m2) program memory one-time prom mask rom 32 kb (16,384 16) (0000h to 3fffh) data memory 447 4 bits capacitor for oscillator ? not provided ( pd17p246m1) any (mask option) ? provided ( pd17p246m2) low-voltage detector note 1 provided any (mask option) v pp pin, operation mode select pin provided not provided instruction execution time note 2 4 s (v dd = 2.2 to 3.6 v) 4 s (v dd = 2.0 to 3.6 v) supply voltage note 2 v dd = 2.2 to 3.6 v v dd = 2.0 to 3.6 v package 30-pin plastic ssop (7.62 mm (300)) notes 1. although the circuit configuration is identical, the electrical characteristics differ depending on the product. 2. when fx = 4 mhz and high-speed mode operation is set.
98 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 in-circuit emulator ie-17k, ie-17k-et note 1 appendix b development tools the following development tools are available to develop the programs for the pd17246 subseries. hardware name remarks the ie-17k and ie-17k-et are in-circuit emulators used in common with the 17k series microcontrollers. the ie-17k and ie-17k-et are connected to the pc-9800 series or ibm pc/at tm compatible machines as the host machine via rs-232c. by using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. a higher level debugging environment can be provided by using the human interface simplehost tm . em board this is an em board for the pd17246 subseries. it can be used alone to evaluate a system (em-17246 note 2 ) or in combination with an in-circuit emulator for debugging. emulation probe the ep-17k30gs is an emulation probe for a 17k series 30-pin shrink sop (mc-5a4). when (ep-17k30gs) used with the ev-9500gt-30 note 3 , it connects an em board to the target system. conversion adapter the ev-9500gt-30 is a conversion adapter for a 30-pin shrink sop (mc-5a4). it is used (ev-9500gt-30 note 3 ) to connect the ep-17k30gs and target system. prom programmer the af-9706, af-9708, and af-9709 are prom programmers corresponding to the pd17p246. (af-9706 note 4 , af-9708 note 4 , by connecting the program adapter pa-17p236 to this prom programmer, the pd17p246 can af-9709 note 4 ) be programmed. program adapter the pa-17p236 is an adapter used to program the pd17p236, and is used in combination (pa-17p236) with the af-9706, af-9708, or af-9709. notes 1. low-cost model: external power supply type 2. this is a product of naito densei machida mfg., co., ltd. (tel +81-45-475-4191) 3. two ev-9500gt-30 units are supplied with the ep-17k30gs. five ev-9500gt-30 units are optionally available as a set. 4. these are products of ando electric co., ltd. (tel: +81-53-576-1560).
99 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 software name outline host machine os supply order code 17k assembler pc-9800 japanese windows tm 3.5" 2hd saa13ra17k (ra17k) series ibm pc/at japanese windows 3.5" 2hc sab13ra17k compatible machine english windows sbb13ra17k device file pc-9800 japanese windows 3.5" 2hd saa13as17246 (as17246) series ibm pc/at japanese windows 3.5" 2hc sab13as17246 compatible machine english windows sbb13as17246 support pc-9800 japanese windows 3.5" 2hd saa13id17k software series ( simplehost ) ibm pc/at japanese windows 3.5" 2hc sab13id17k compatible machine english windows sbb13id17k the ra17k is an assembler common to 17k series products. when developing the programs of devices, ra17k is used in combination with a device file (as17225). the as17246 is a device file for the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246, and is used in combination with an assembler for the 17k series (ra17k). simplehost is a software package that enables a human interface on windows when a program is developed by using an in-circuit emulator and a personal computer.
100 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
101 data sheet u15002ej1v0ds pd17240, 17241, 17242, 17243, 17244, 17245, 17246 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v?lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
simplehost is a trademark of nec electronics corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. pd17240, 17241, 17242, 17243, 17244, 17245, 17246 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of january, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec e lectronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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